From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZYDxN-0004jJ-Ma for qemu-devel@nongnu.org; Sat, 05 Sep 2015 09:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZYDxJ-0006j0-M2 for qemu-devel@nongnu.org; Sat, 05 Sep 2015 09:56:37 -0400 Received: from mail-vk0-f53.google.com ([209.85.213.53]:36597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZYDxJ-0006iq-Id for qemu-devel@nongnu.org; Sat, 05 Sep 2015 09:56:33 -0400 Received: by vkbc123 with SMTP id c123so24581305vkb.3 for ; Sat, 05 Sep 2015 06:56:32 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <55EAF062.4070209@virgin.net> References: <1441272453-23964-1-git-send-email-user@mike-desktop> <55EAD1F8.60107@virgin.net> <55EAF062.4070209@virgin.net> From: Peter Maydell Date: Sat, 5 Sep 2015 14:56:13 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH] ARM targets: added ARM_FEATURE for Thumb-exception bit in system control register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mike Haben Cc: QEMU Developers On 5 September 2015 at 14:38, Mike Haben wrote: > Hi Peter, > You're quite right, on reading some more I see the correspondence with V7. > However... while reading up on the Cortex-M3/4/7, I also found > "Only Thumb and Thumb-2 instruction sets are supported in Cortex-M > architectures, but the legacy 32-bit ARM instruction set isn't supported". > Ugh - to avoid storing up a problem for the future, I think I better think > it out again! M profile exception handling is completely different to A/R profile, and does not use this function at all (it is done via arm_v7m_cpu_do_interrupt()). So that isn't a problem. (In fact M profile doesn't even have an SCTLR register.) thanks -- PMM