Re: [Qemu-devel] [PATCH v5 13/28] fpu/softfloat: Partial support for ARM Alternative half-precision

[Peter Maydell <peter.maydell@linaro.org>]

On 14 May 2018 at 23:12, Richard Henderson <richard.henderson@linaro.org> wrote:
> From: Alex Bennée <alex.bennee@linaro.org>
>
> For float16 ARM supports an alternative half-precision format which
> sacrifices the ability to represent NaN/Inf in return for a higher
> dynamic range.  The new FloatFmt flag, arm_althp, is then used to
> modify the behaviour of canonicalize and round_canonical with respect
> to representation and exception raising.
>
> Usage of this new flag waits until we re-factor float-to-float conversions.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
> ---
> v3
>   - squash NaN to 0 if destination is AHP F16
> v4
>   - handle inf -> ahp max in float_to_float not round_canonical
>   - assert no nan and inf for ahp in round_canonical
>   - check ahp before snan in float_to_float
> v5
>   - split out canonicalize and round_canonical changes from the rest
> ---
>  fpu/softfloat.c | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 41253c6749..55d0d01ec3 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -220,8 +220,10 @@ typedef struct {
>   *   frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT
>   * The following are computed based the size of fraction
>   *   frac_lsb: least significant bit of fraction
> - *   fram_lsbm1: the bit bellow the least significant bit (for rounding)
> + *   frac_lsbm1: the bit bellow the least significant bit (for rounding)

"below"

>   *   round_mask/roundeven_mask: masks used for rounding
> + * The following optional modifiers are available:
> + *   arm_althp: handle ARM Alternative Half Precision
>   */

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM