From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RLN28-0002Jt-UE for qemu-devel@nongnu.org; Tue, 01 Nov 2011 18:42:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RLN27-0006FU-4o for qemu-devel@nongnu.org; Tue, 01 Nov 2011 18:42:16 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:47800) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RLN26-0006FA-QN for qemu-devel@nongnu.org; Tue, 01 Nov 2011 18:42:15 -0400 Received: by qadc12 with SMTP id c12so7866761qad.4 for ; Tue, 01 Nov 2011 15:42:14 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1319823613-22903-1-git-send-email-rabin@rab.in> Date: Tue, 1 Nov 2011 22:42:14 +0000 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] arm_gic: handle banked enable bits for per-cpu interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Rabin Vincent Cc: Anthony Liguori , qemu-devel@nongnu.org On 1 November 2011 22:31, Peter Maydell wrote: > On 28 October 2011 18:40, Rabin Vincent wrote: >> The first enable set/clear register (which controls the PPIs and SGIs) >> is supposed to be banked for each processor. =C2=A0Currently it is just >> handled globally and this prevents recent SMP Linux kernels from >> booting, because CPU0 stops receiving localtimer interrupts when CPU1 >> disables them locally. > Reviewed-by: Peter Maydell This has just missed the 1.0rc0 deadline but as it's a bug fix we can put it into rc1. -- PMM