From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48572) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aeASy-0000G3-Og for qemu-devel@nongnu.org; Thu, 10 Mar 2016 18:58:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aeASx-00046a-IS for qemu-devel@nongnu.org; Thu, 10 Mar 2016 18:58:04 -0500 Received: from mail-vk0-x22a.google.com ([2607:f8b0:400c:c05::22a]:32801) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aeASx-000469-Ck for qemu-devel@nongnu.org; Thu, 10 Mar 2016 18:58:03 -0500 Received: by mail-vk0-x22a.google.com with SMTP id k1so116056895vkb.0 for ; Thu, 10 Mar 2016 15:58:03 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <56E1C9DA.7010400@tribudubois.net> References: <56E1C9DA.7010400@tribudubois.net> From: Peter Maydell Date: Fri, 11 Mar 2016 06:57:43 +0700 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 12/12] i.MX: Add sabrelite i.MX6 emulation. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jean-Christophe DUBOIS Cc: QEMU Developers , Peter Crosthwaite On 11 March 2016 at 02:24, Jean-Christophe DUBOIS wro= te: > Le 10/03/2016 11:38, Peter Maydell a =C3=A9crit : >> >> On 2 March 2016 at 05:27, Jean-Christophe Dubois >> wrote: >>> >>> The sabrelite supports one SPI FLASH memory on SPI1 >>> >>> Signed-off-by: Jean-Christophe Dubois >>> --- >>> >>> + >>> + { >>> + /* Add the sst25vf016b NOR FLASH memory to first SPI */ >>> + Object *spi_dev; >>> + >>> + spi_dev =3D object_resolve_path_component(OBJECT(&s->soc), >>> "spi1"); >>> + if (spi_dev) { >>> + SSIBus *spi_bus; >>> + >>> + spi_bus =3D (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), >>> "spi"); >> >> This looks odd. You should just be able to do >> spi_bus =3D (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), "spi1"); >> without using object_resolve_path_component() to try to find an >> SPI device object, because your SoC device should have alias properties >> which provide access to its SPI subcomponents' SPI buses. >> See hw/arm/xlnx-ep108.c for an example of the board code for this and >> hw/arm/xlnx-zynqmp.c for the SoC code which calls >> object_property_add_alias() to set up the aliases. > > > I certainly could do as you proposed. > > The problem is that I also need the spi_dev device for the > sysbus_connect_irq() call below. > > My spi_dev is referenced as "spi1" in the i.MX6 doc and I added a 'spi1" > property for it in the i.MX6 soc. > > Once I have the spi_dev device it is trivial to retrieve the spi_bus > attached to it. > > So, yes this is not in line with what is done in xlnx-zynqmp.c but the ne= ed > is a bit different. I think the SoC should probably have an externally-facing IRQ line which it wires up internally to the SPI's IRQ line. (This corresponds basically to what happens in h/w -- the SoC's interfaces are defined by it even though many of them may be directly wired up to some internal component it has, but from outside the SoC you don't get access to the whole of the internal component.) thanks -- PMM