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From: Peter Maydell <peter.maydell@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Magnus Kulke <magnuskulke@linux.microsoft.com>
Subject: Re: [PULL 28/35] target/i386/mshv: Implement mshv_vcpu_run()
Date: Tue, 21 Oct 2025 16:27:46 +0100	[thread overview]
Message-ID: <CAFEAcA-NPDB7TMFeGJqaYJUZG13Lkxfc7o8yUbJfighH_xp8Dg@mail.gmail.com> (raw)
In-Reply-To: <20251009075026.505715-29-pbonzini@redhat.com>

On Thu, 9 Oct 2025 at 08:56, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> From: Magnus Kulke <magnuskulke@linux.microsoft.com>
>
> Add the main vCPU execution loop for MSHV using the MSHV_RUN_VP ioctl.
>
> The execution loop handles guest entry and VM exits. There are handlers for
> memory r/w, PIO and MMIO to which the exit events are dispatched.
>
> In case of MMIO the i386 instruction decoder/emulator is invoked to
> perform the operation in user space.

Hi; Coverity complains about this code (CID 1641395):

> +static int handle_pio_str(CPUState *cpu, hv_x64_io_port_intercept_message *info)
> +{
> +    uint8_t access_type = info->header.intercept_access_type;
> +    uint16_t port = info->port_number;
> +    bool repop = info->access_info.rep_prefix == 1;
> +    size_t repeat = repop ? info->rcx : 1;
> +    size_t insn_len = info->header.instruction_length;
> +    bool direction_flag;
> +    uint32_t reg_names[3];
> +    uint64_t reg_values[3];
> +    int ret;
> +    X86CPU *x86_cpu = X86_CPU(cpu);
> +    CPUX86State *env = &x86_cpu->env;
> +
> +    ret = fetch_guest_state(cpu);
> +    if (ret < 0) {
> +        error_report("Failed to fetch guest state");
> +        return -1;
> +    }
> +
> +    direction_flag = (env->eflags & DESC_E_MASK) != 0;
> +
> +    if (access_type == HV_X64_INTERCEPT_ACCESS_TYPE_WRITE) {
> +        ret = handle_pio_str_write(cpu, info, repeat, port, direction_flag);
> +        if (ret < 0) {
> +            error_report("Failed to handle pio str write");
> +            return -1;
> +        }
> +        reg_names[0] = HV_X64_REGISTER_RSI;
> +        reg_values[0] = info->rsi;
> +    } else {
> +        ret = handle_pio_str_read(cpu, info, repeat, port, direction_flag);

We set ret to the return value here, but there's no error check.
Should there be one here?

Coverity complains because we assign to 'ret' here but
then never read it again before we overwrite it with
the call to set_x64_registers().

> +        reg_names[0] = HV_X64_REGISTER_RDI;
> +        reg_values[0] = info->rdi;
> +    }
> +
> +    reg_names[1] = HV_X64_REGISTER_RIP;
> +    reg_values[1] = info->header.rip + insn_len;
> +    reg_names[2] = HV_X64_REGISTER_RAX;
> +    reg_values[2] = info->rax;
> +
> +    ret = set_x64_registers(cpu, reg_names, reg_values);
> +    if (ret < 0) {
> +        error_report("Failed to set x64 registers");
> +        return -1;
> +    }
> +
> +    cpu->accel->dirty = false;
> +
> +    return 0;
> +}


thanks
-- PMM


  reply	other threads:[~2025-10-21 15:28 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-09  7:49 [PULL 00/35] i386 (MSHV, migration) and Rust changes for 2025-10-09 Paolo Bonzini
2025-10-09  7:49 ` [PULL 01/35] subprojects: Remove version number from .gitignore Paolo Bonzini
2025-10-09  7:49 ` [PULL 02/35] subprojects: add glib-sys-rs Paolo Bonzini
2025-10-09  7:49 ` [PULL 03/35] rust: use glib-sys Paolo Bonzini
2025-10-09  7:49 ` [PULL 04/35] build-sys: default to host vendor for rust target triple Paolo Bonzini
2025-10-09  7:49 ` [PULL 05/35] target/i386: add compatibility property for arch_capabilities Paolo Bonzini
2025-10-09  7:49 ` [PULL 06/35] target/i386: add compatibility property for pdcm feature Paolo Bonzini
2025-10-09  7:49 ` [PULL 07/35] accel: Add Meson and config support for MSHV accelerator Paolo Bonzini
2025-10-09  7:49 ` [PULL 08/35] target/i386/emulate: Allow instruction decoding from stream Paolo Bonzini
2025-10-09  7:49 ` [PULL 09/35] target/i386/mshv: Add x86 decoder/emu implementation Paolo Bonzini
2025-10-09  7:50 ` [PULL 10/35] hw/intc: Generalize APIC helper names from kvm_* to accel_* Paolo Bonzini
2025-11-03 21:43   ` Cédric Le Goater
2025-11-05 15:24     ` Magnus Kulke
2025-11-06 10:51       ` Cédric Le Goater
2025-10-09  7:50 ` [PULL 11/35] include/hw/hyperv: Add MSHV ABI header definitions Paolo Bonzini
2025-10-09  7:50 ` [PULL 12/35] linux-headers/linux: Add mshv.h headers Paolo Bonzini
2025-10-09  7:50 ` [PULL 13/35] accel/mshv: Add accelerator skeleton Paolo Bonzini
2025-10-09  7:50 ` [PULL 14/35] accel/mshv: Register memory region listeners Paolo Bonzini
2025-10-09  7:50 ` [PULL 15/35] accel/mshv: Initialize VM partition Paolo Bonzini
2025-10-09  7:50 ` [PULL 16/35] accel/mshv: Add vCPU creation and execution loop Paolo Bonzini
2025-10-21 15:48   ` Peter Maydell
2025-10-09  7:50 ` [PULL 17/35] accel/mshv: Add vCPU signal handling Paolo Bonzini
2025-10-09  7:50 ` [PULL 18/35] target/i386/mshv: Add CPU create and remove logic Paolo Bonzini
2025-10-09  7:50 ` [PULL 19/35] target/i386/mshv: Implement mshv_store_regs() Paolo Bonzini
2025-10-09  7:50 ` [PULL 20/35] target/i386/mshv: Implement mshv_get_standard_regs() Paolo Bonzini
2025-10-09  7:50 ` [PULL 21/35] target/i386/mshv: Implement mshv_get_special_regs() Paolo Bonzini
2025-10-09  7:50 ` [PULL 22/35] target/i386/mshv: Implement mshv_arch_put_registers() Paolo Bonzini
2025-10-09  7:50 ` [PULL 23/35] target/i386/mshv: Set local interrupt controller state Paolo Bonzini
2025-10-09  7:50 ` [PULL 24/35] target/i386/mshv: Register CPUID entries with MSHV Paolo Bonzini
2025-10-09  7:50 ` [PULL 25/35] target/i386/mshv: Register MSRs " Paolo Bonzini
2025-10-09  7:50 ` [PULL 26/35] target/i386/mshv: Integrate x86 instruction decoder/emulator Paolo Bonzini
2025-10-09  7:50 ` [PULL 27/35] target/i386/mshv: Write MSRs to the hypervisor Paolo Bonzini
2025-10-09  7:50 ` [PULL 28/35] target/i386/mshv: Implement mshv_vcpu_run() Paolo Bonzini
2025-10-21 15:27   ` Peter Maydell [this message]
2025-11-09 13:10   ` Bernhard Beschow
2025-10-09  7:50 ` [PULL 29/35] accel/mshv: Handle overlapping mem mappings Paolo Bonzini
2025-10-09  7:50 ` [PULL 30/35] qapi/accel: Allow to query mshv capabilities Paolo Bonzini
2025-10-09  7:50 ` [PULL 31/35] target/i386/mshv: Use preallocated page for hvcall Paolo Bonzini
2025-10-09  7:50 ` [PULL 32/35] docs: Add mshv to documentation Paolo Bonzini
2025-10-09  7:50 ` [PULL 33/35] MAINTAINERS: Add maintainers for mshv accelerator Paolo Bonzini
2025-10-09  7:50 ` [PULL 34/35] tests/docker: make --enable-rust overridable with EXTRA_CONFIGURE_OPTS Paolo Bonzini
2025-10-09  7:50 ` [PULL 35/35] rust: fix path to rust_root_crate.sh Paolo Bonzini
2025-10-09 16:23 ` [PULL 00/35] i386 (MSHV, migration) and Rust changes for 2025-10-09 Richard Henderson

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