From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOBtl-0001cZ-5r for qemu-devel@nongnu.org; Fri, 05 Apr 2013 15:02:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UOBtj-0000RU-A7 for qemu-devel@nongnu.org; Fri, 05 Apr 2013 15:02:05 -0400 Received: from mail-lb0-f182.google.com ([209.85.217.182]:40679) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UOBtj-0000RG-3A for qemu-devel@nongnu.org; Fri, 05 Apr 2013 15:02:03 -0400 Received: by mail-lb0-f182.google.com with SMTP id z13so4094586lbh.27 for ; Fri, 05 Apr 2013 12:02:02 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <475b23a3c56ec5ee1a8652f33e0a12d0bb4ac7f6.1364962908.git.peter.crosthwaite@xilinx.com> From: Peter Maydell Date: Fri, 5 Apr 2013 20:01:41 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH arm-devs v1 15/15] xilinx_spips: lqspi: Fix byte/misaligned access List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: qemu-devel@nongnu.org On 3 April 2013 05:33, Peter Crosthwaite wrote: > The LQSPI bus attachment supports byte/halfword and misaligned > accesses. Fixed. Refactored the LQSPI cache to be byte-wise > instead of word wise accordingly. > > Signed-off-by: Peter Crosthwaite > --- > > hw/xilinx_spips.c | 31 +++++++++++++++++-------------- > 1 files changed, 17 insertions(+), 14 deletions(-) > > diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c > index 32d8db8..cb45a9c 100644 > --- a/hw/xilinx_spips.c > +++ b/hw/xilinx_spips.c > @@ -160,7 +160,7 @@ typedef struct { > typedef struct { > XilinxSPIPS parent_obj; > > - uint32_t lqspi_buf[LQSPI_CACHE_SIZE]; > + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; Is it really right that this buffer isn't in the vmstate, by the way? > hwaddr lqspi_cached_addr; > } XilinxQSPIPS; -- PMM