From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>,
Michael Rolnik <mrolnik@gmail.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits
Date: Mon, 12 Apr 2021 10:07:54 +0100 [thread overview]
Message-ID: <CAFEAcA-ccgKHzgxvK_Wb8hD4ce=KYu2NbZ-3UGhaW447JTVgAg@mail.gmail.com> (raw)
In-Reply-To: <a57eed31-78c3-8ea5-579a-cb4edd1afbd3@linaro.org>
On Sun, 11 Apr 2021 at 16:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/10/21 10:24 AM, Michael Rolnik wrote:
> > Please review.
>
>
> The first 256b is i/o, the next 768b are ram. But having changed the page
> size, it should mean that the first 1k are now treated as i/o.
>
> We do have a path by which instructions in i/o pages can be executed. This
> happens on some ARM board setups during cold boot. But we do not save those
> translations, so they run much much slower than it should.
>
> But perhaps in the case of AVR, "much much slower" really isn't visible?
>
> In general, I think changing the page size is wrong. I also assume that
> migration is largely irrelevant to this target.
Migration is irrelevant, but every target benefits from snapshot
save-and-restore, and I think that uses the same codepaths ?
-- PMM
next prev parent reply other threads:[~2021-04-12 9:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-20 22:09 [PATCH 0/1] Set AVR TARGET_PAGE_BITS to be 10 instead of 8 Michael Rolnik
2021-03-20 22:09 ` [PATCH 1/1] Set TARGET_PAGE_BITS to be 10 instead of 8 bits Michael Rolnik
2021-03-23 12:46 ` Dr. David Alan Gilbert
2021-03-23 20:11 ` Michael Rolnik
2021-03-23 20:28 ` Michael Rolnik
2021-04-10 17:24 ` Michael Rolnik
2021-04-11 15:12 ` Richard Henderson
2021-04-12 9:07 ` Peter Maydell [this message]
2021-04-27 17:52 ` Dr. David Alan Gilbert
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