* [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018
@ 2018-08-14 18:16 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 01/19] MAINTAINERS: Update target/mips maintainer's email addresses Aleksandar Markovic
` (19 more replies)
0 siblings, 20 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
The following changes since commit 38441756b70eec5807b5f60dad11a93a91199866:
Update version for v3.0.0 release (2018-08-14 16:38:43 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-aug-14-2018
for you to fetch changes up to 20d4e01b6486b15d1f3d9ff2d51bba2bf00ebf94:
qemu-doc: Amend MIPS-related items (2018-08-14 19:59:03 +0200)
----------------------------------------------------------------
MIPS queue for QEMU upstream, August 14, 2018
This is the first part of nanoMIPS support for QEMU. It contains
various fixes and improvements that are related to nanoMIPS support,
or are discovered while working on nanoMIPS support. Most of them are
fairly simple changes, but each of them has its own significance and
importance for nanoMIPS support.
The second part that contains QEMU support for core nanoMIPS
functionality will remain under review for some time.
The third part that mainly contains Linux user support will likely
remain under review for some longer period.
----------------------------------------------------------------
Aleksandar Markovic (9):
MAINTAINERS: Update target/mips maintainer's email addresses
target/mips: Avoid case statements formulated by ranges - part 1
target/mips: Mark switch fallthroughs with interpretable comments
target/mips: Fix two instances of shadow variables
target/mips: Update some CP0 registers bit definitions
elf: Remove duplicate preprocessor constant definition
elf: Add ELF flags for MIPS machine variants
linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
qemu-doc: Amend MIPS-related items
Aleksandar Rikalo (5):
target/mips: Avoid case statements formulated by ranges - part 2
target/mips: Add support for availability control via bit XNP
target/mips: Add support for availability control via bit MT
target/mips: Fix MT ASE instructions' availability control
linux-user: Add preprocessor availability control to some syscalls
Stefan Markovic (3):
target/mips: Add CP0 BadInstrX register
target/mips: Implement CP0 Config1.WR bit functionality
target/mips: Add gen_op_addr_addi()
Yongbok Kim (2):
target/mips: Don't update BadVAddr register in Debug Mode
target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
.mailmap | 7 +-
MAINTAINERS | 9 +-
include/elf.h | 24 ++-
linux-user/mips/syscall_nr.h | 9 +
linux-user/mips64/syscall_nr.h | 18 ++
linux-user/strace.c | 14 +-
linux-user/syscall.c | 29 +++
qemu-doc.texi | 13 +-
target/mips/cpu.h | 162 ++++++++-------
target/mips/helper.c | 4 +-
target/mips/internal.h | 9 +-
target/mips/machine.c | 5 +-
target/mips/op_helper.c | 12 +-
target/mips/translate.c | 443 ++++++++++++++++++++++++++++++++++-------
14 files changed, 598 insertions(+), 160 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 01/19] MAINTAINERS: Update target/mips maintainer's email addresses
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 02/19] target/mips: Avoid case statements formulated by ranges - part 1 Aleksandar Markovic
` (18 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
.mailmap | 7 +++++--
MAINTAINERS | 9 +++++----
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/.mailmap b/.mailmap
index 778a4d4..2c2b9b1 100644
--- a/.mailmap
+++ b/.mailmap
@@ -12,8 +12,11 @@ Fabrice Bellard <fabrice@bellard.org> bellard <bellard@c046a42c-6fe2-441c-8c8c-7
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Jocelyn Mayer <l_indien@magic.fr> j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
Paul Brook <paul@codesourcery.com> pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
-Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
-Paul Burton <paul.burton@mips.com> <paul@archlinuxmips.org>
+Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
+Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
+Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
+Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
+Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
Thiemo Seufer <ths@networkno.de> ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
malc <av1474@comtv.ru> malc <malc@c046a42c-6fe2-441c-8c8c-71466251a162>
diff --git a/MAINTAINERS b/MAINTAINERS
index 666e936..7130807 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -187,7 +187,7 @@ F: disas/microblaze.c
MIPS
M: Aurelien Jarno <aurelien@aurel32.net>
-M: Aleksandar Markovic <aleksandar.markovic@mips.com>
+M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Maintained
F: target/mips/
F: hw/mips/
@@ -718,7 +718,7 @@ S: Maintained
F: hw/mips/mips_malta.c
Mipssim
-M: Aleksandar Markovic <aleksandar.markovic@mips.com>
+M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
@@ -729,14 +729,15 @@ S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
-M: Aleksandar Markovic <aleksandar.markovic@mips.com>
+M: Aleksandar Markovic <amarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
+
F: include/hw/isa/vt82c686.h
Boston
-M: Paul Burton <paul.burton@mips.com>
+M: Paul Burton <pburton@wavecomp.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 02/19] target/mips: Avoid case statements formulated by ranges - part 1
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 01/19] MAINTAINERS: Update target/mips maintainer's email addresses Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 03/19] target/mips: Avoid case statements formulated by ranges - part 2 Aleksandar Markovic
` (17 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 249 ++++++++++++++++++++++++++++++++++++++----------
1 file changed, 200 insertions(+), 49 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 20b43c0..051dda5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5494,7 +5494,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5504,7 +5511,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ...7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -5630,7 +5644,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@@ -5701,7 +5718,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -6167,7 +6189,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6177,7 +6206,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6315,7 +6351,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
/* ignored */
rn = "CacheErr";
break;
@@ -6381,7 +6420,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -6842,7 +6886,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6852,7 +6903,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6975,7 +7033,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 27:
switch (sel) {
/* ignored */
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@@ -7040,7 +7101,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -7497,7 +7563,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7507,7 +7580,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7641,7 +7721,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
- case 0 ... 3:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
/* ignored */
rn = "CacheErr";
break;
@@ -7707,7 +7790,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
- case 2 ... 7:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -7843,7 +7931,14 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
break;
case 16:
switch (sel) {
- case 0 ... 7:
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
break;
default:
@@ -17231,7 +17326,10 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
case OPC_LSA:
gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break;
- case OPC_MULT ... OPC_DIVU:
+ case OPC_MULT:
+ case OPC_MULTU:
+ case OPC_DIV:
+ case OPC_DIVU:
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_MUL:
@@ -17291,7 +17389,11 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI);
}
break;
- case OPC_DMULT ... OPC_DDIVU:
+ case OPC_DMULT:
+ case OPC_DMULTU:
+ case OPC_DDIV:
+ case OPC_DDIVU:
+
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_DMUL:
@@ -17370,7 +17472,10 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_muldiv(ctx, op1, 0, rs, rt);
break;
#if defined(TARGET_MIPS64)
- case OPC_DMULT ... OPC_DDIVU:
+ case OPC_DMULT:
+ case OPC_DMULTU:
+ case OPC_DDIV:
+ case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
@@ -17437,7 +17542,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
- case OPC_ADD ... OPC_SUBU:
+ case OPC_ADD:
+ case OPC_ADDU:
+ case OPC_SUB:
+ case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_SLLV: /* Shifts */
@@ -17473,7 +17581,11 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break;
- case OPC_TGE ... OPC_TEQ: /* Traps */
+ case OPC_TGE: /* Traps */
+ case OPC_TGEU:
+ case OPC_TLT:
+ case OPC_TLTU:
+ case OPC_TEQ:
case OPC_TNE:
check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1);
@@ -17549,7 +17661,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
- case OPC_DADD ... OPC_DSUBU:
+ case OPC_DADD:
+ case OPC_DADDU:
+ case OPC_DSUB:
+ case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt);
@@ -17607,8 +17722,10 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) {
- case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
- case OPC_MSUB ... OPC_MSUBU:
+ case OPC_MADD: /* Multiply and add/sub */
+ case OPC_MADDU:
+ case OPC_MSUB:
+ case OPC_MSUBU:
check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
@@ -17705,7 +17822,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
- case OPC_ALIGN ... OPC_ALIGN_END:
+ case OPC_ALIGN:
+ case OPC_ALIGN_END:
gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
@@ -17730,7 +17848,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
- case OPC_DALIGN ... OPC_DALIGN_END:
+ case OPC_DALIGN:
+ case OPC_DALIGN_END:
gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
@@ -17759,9 +17878,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
- case OPC_MOD_G_2E ... OPC_MODU_G_2E:
- case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
+ case OPC_DIV_G_2E:
+ case OPC_DIVU_G_2E:
+ case OPC_MOD_G_2E:
+ case OPC_MODU_G_2E:
+ case OPC_MULT_G_2E:
+ case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
@@ -18025,9 +18147,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
- case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
- case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
+ case OPC_DDIV_G_2E:
+ case OPC_DDIVU_G_2E:
+ case OPC_DMULT_G_2E:
+ case OPC_DMULTU_G_2E:
+ case OPC_DMOD_G_2E:
+ case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -18289,18 +18414,25 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
*/
if (ctx->eva) {
switch (op1) {
- case OPC_LWLE ... OPC_LWRE:
+ case OPC_LWLE:
+ case OPC_LWRE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
- case OPC_LBUE ... OPC_LHUE:
- case OPC_LBE ... OPC_LWE:
+ case OPC_LBUE:
+ case OPC_LHUE:
+ case OPC_LBE:
+ case OPC_LHE:
+ case OPC_LLE:
+ case OPC_LWE:
check_cp0_enabled(ctx);
gen_ld(ctx, op1, rt, rs, imm);
return;
- case OPC_SWLE ... OPC_SWRE:
+ case OPC_SWLE:
+ case OPC_SWRE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
- case OPC_SBE ... OPC_SHE:
+ case OPC_SBE:
+ case OPC_SHE:
case OPC_SWE:
check_cp0_enabled(ctx);
gen_st(ctx, op1, rt, rs, imm);
@@ -18332,7 +18464,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_BSHFL:
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
- case OPC_ALIGN ... OPC_ALIGN_END:
+ case OPC_ALIGN:
+ case OPC_ALIGN_END:
case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@@ -18344,8 +18477,12 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DEXTM ... OPC_DEXT:
- case OPC_DINSM ... OPC_DINS:
+ case OPC_DEXTM:
+ case OPC_DEXTU:
+ case OPC_DEXT:
+ case OPC_DINSM:
+ case OPC_DINSU:
+ case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
@@ -18353,7 +18490,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DBSHFL:
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
- case OPC_DALIGN ... OPC_DALIGN_END:
+ case OPC_DALIGN:
+ case OPC_DALIGN_END:
case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@@ -19584,7 +19722,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
}
break;
- case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
+ case OPC_TGEI: /* REGIMM traps */
+ case OPC_TGEIU:
+ case OPC_TLTI:
+ case OPC_TLTIU:
+ case OPC_TEQI:
+
case OPC_TNEI:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
@@ -19759,7 +19902,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm);
break;
- case OPC_J ... OPC_JAL: /* Jump */
+ case OPC_J: /* Jump */
+ case OPC_JAL:
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break;
@@ -19826,15 +19970,20 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_LWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Fallthrough */
- case OPC_LB ... OPC_LH:
- case OPC_LW ... OPC_LHU:
+ case OPC_LB:
+ case OPC_LH:
+ case OPC_LW:
+ case OPC_LWPC:
+ case OPC_LBU:
+ case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SWL:
case OPC_SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
- case OPC_SB ... OPC_SH:
+ case OPC_SB:
+ case OPC_SH:
case OPC_SW:
gen_st(ctx, op, rt, rs, imm);
break;
@@ -20105,7 +20254,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
- case OPC_LDL ... OPC_LDR:
+ case OPC_LDL:
+ case OPC_LDR:
case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
@@ -20115,7 +20265,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm);
break;
- case OPC_SDL ... OPC_SDR:
+ case OPC_SDL:
+ case OPC_SDR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
case OPC_SD:
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 03/19] target/mips: Avoid case statements formulated by ranges - part 2
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 01/19] MAINTAINERS: Update target/mips maintainer's email addresses Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 02/19] target/mips: Avoid case statements formulated by ranges - part 1 Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 04/19] target/mips: Mark switch fallthroughs with interpretable comments Aleksandar Markovic
` (16 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Remove "range style" case statements to make code analysis easier.
This patch handles cases when the values in the range in question
were not properly defined.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 78 ++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 71 insertions(+), 7 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 051dda5..b944ea2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -902,8 +902,21 @@ enum {
OPC_MTTR = (0x0C << 21) | OPC_CP0,
OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
OPC_C0 = (0x10 << 21) | OPC_CP0,
- OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
- OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
+ OPC_C0_1 = (0x11 << 21) | OPC_CP0,
+ OPC_C0_2 = (0x12 << 21) | OPC_CP0,
+ OPC_C0_3 = (0x13 << 21) | OPC_CP0,
+ OPC_C0_4 = (0x14 << 21) | OPC_CP0,
+ OPC_C0_5 = (0x15 << 21) | OPC_CP0,
+ OPC_C0_6 = (0x16 << 21) | OPC_CP0,
+ OPC_C0_7 = (0x17 << 21) | OPC_CP0,
+ OPC_C0_8 = (0x18 << 21) | OPC_CP0,
+ OPC_C0_9 = (0x19 << 21) | OPC_CP0,
+ OPC_C0_A = (0x1A << 21) | OPC_CP0,
+ OPC_C0_B = (0x1B << 21) | OPC_CP0,
+ OPC_C0_C = (0x1C << 21) | OPC_CP0,
+ OPC_C0_D = (0x1D << 21) | OPC_CP0,
+ OPC_C0_E = (0x1E << 21) | OPC_CP0,
+ OPC_C0_F = (0x1F << 21) | OPC_CP0,
};
/* MFMC0 opcodes */
@@ -12490,10 +12503,22 @@ enum {
/* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */
enum {
ADDIUPC_00 = 0x00,
+ ADDIUPC_01 = 0x01,
+ ADDIUPC_02 = 0x02,
+ ADDIUPC_03 = 0x03,
+ ADDIUPC_04 = 0x04,
+ ADDIUPC_05 = 0x05,
+ ADDIUPC_06 = 0x06,
ADDIUPC_07 = 0x07,
AUIPC = 0x1e,
ALUIPC = 0x1f,
LWPC_08 = 0x08,
+ LWPC_09 = 0x09,
+ LWPC_0A = 0x0A,
+ LWPC_0B = 0x0B,
+ LWPC_0C = 0x0C,
+ LWPC_0D = 0x0D,
+ LWPC_0E = 0x0E,
LWPC_0F = 0x0F,
};
@@ -12928,12 +12953,16 @@ enum {
R6_LWM16 = 0x02,
R6_JRC16 = 0x03,
MOVEP = 0x04,
+ MOVEP_05 = 0x05,
+ MOVEP_06 = 0x06,
MOVEP_07 = 0x07,
R6_XOR16 = 0x08,
R6_OR16 = 0x09,
R6_SWM16 = 0x0a,
JALRC16 = 0x0b,
MOVEP_0C = 0x0c,
+ MOVEP_0D = 0x0d,
+ MOVEP_0E = 0x0e,
MOVEP_0F = 0x0f,
JRCADDIUSP = 0x13,
R6_BREAK16 = 0x1b,
@@ -13251,8 +13280,14 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
}
break;
- case MOVEP ... MOVEP_07:
- case MOVEP_0C ... MOVEP_0F:
+ case MOVEP:
+ case MOVEP_05:
+ case MOVEP_06:
+ case MOVEP_07:
+ case MOVEP_0C:
+ case MOVEP_0D:
+ case MOVEP_0E:
+ case MOVEP_0F:
{
int enc_dest = uMIPS_RD(ctx->opcode);
int enc_rt = uMIPS_RS2(ctx->opcode);
@@ -15230,7 +15265,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & ISA_MIPS32R6) {
/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
switch ((ctx->opcode >> 16) & 0x1f) {
- case ADDIUPC_00 ... ADDIUPC_07:
+ case ADDIUPC_00:
+ case ADDIUPC_01:
+ case ADDIUPC_02:
+ case ADDIUPC_03:
+ case ADDIUPC_04:
+ case ADDIUPC_05:
+ case ADDIUPC_06:
+ case ADDIUPC_07:
gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt);
break;
case AUIPC:
@@ -15239,7 +15281,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case ALUIPC:
gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt);
break;
- case LWPC_08 ... LWPC_0F:
+ case LWPC_08:
+ case LWPC_09:
+ case LWPC_0A:
+ case LWPC_0B:
+ case LWPC_0C:
+ case LWPC_0D:
+ case LWPC_0E:
+ case LWPC_0F:
gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt);
break;
default:
@@ -19790,7 +19839,22 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_cp0(env, ctx, op1, rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
- case OPC_C0_FIRST ... OPC_C0_LAST:
+ case OPC_C0:
+ case OPC_C0_1:
+ case OPC_C0_2:
+ case OPC_C0_3:
+ case OPC_C0_4:
+ case OPC_C0_5:
+ case OPC_C0_6:
+ case OPC_C0_7:
+ case OPC_C0_8:
+ case OPC_C0_9:
+ case OPC_C0_A:
+ case OPC_C0_B:
+ case OPC_C0_C:
+ case OPC_C0_D:
+ case OPC_C0_E:
+ case OPC_C0_F:
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif /* !CONFIG_USER_ONLY */
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 04/19] target/mips: Mark switch fallthroughs with interpretable comments
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (2 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 03/19] target/mips: Avoid case statements formulated by ranges - part 2 Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 05/19] target/mips: Fix two instances of shadow variables Aleksandar Markovic
` (15 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mark switch fallthroughs with comments, in cases fallthroughs
are intentional.
The comments "/* fall through */" are interpreted by compilers and
other tools, and they will not issue warnings in such cases. For gcc,
the warning is turnend on by -Wimplicit-fallthrough. With this patch,
there will be no such warnings in target/mips directory. If such
warning appears in future, it should be checked if it is intentional,
and, if yes, marked with a comment similar to those from this patch.
The comment must be just before next "case", otherwise gcc won't
understand it.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b944ea2..3dd66b6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -14290,8 +14290,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case SDP:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- /* Fallthrough */
#endif
+ /* fall through */
case LWP:
case SWP:
gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -14301,8 +14301,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case SDM:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- /* Fallthrough */
#endif
+ /* fall through */
case LWM32:
case SWM32:
gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -20087,6 +20087,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_MTHC1:
check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
+ /* fall through */
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 05/19] target/mips: Fix two instances of shadow variables
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (3 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 04/19] target/mips: Mark switch fallthroughs with interpretable comments Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 06/19] target/mips: Update some CP0 registers bit definitions Aleksandar Markovic
` (14 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Fix two instances of shadow variables. This cleans up entire file
translate.c from shadow variables.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3dd66b6..2b70d1b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -13276,7 +13276,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
} else {
/* JRC16 */
- int rs = extract32(ctx->opcode, 5, 5);
+ rs = extract32(ctx->opcode, 5, 5);
gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
}
break;
@@ -15298,7 +15298,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
} else {
/* ADDIUPC */
int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
- int offset = SIMM(ctx->opcode, 0, 23) << 2;
+ offset = SIMM(ctx->opcode, 0, 23) << 2;
gen_addiupc(ctx, reg, offset, 0, 0);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 06/19] target/mips: Update some CP0 registers bit definitions
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (4 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 05/19] target/mips: Fix two instances of shadow variables Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 07/19] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
` (13 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 157 ++++++++++++++++++++++++++++++------------------------
1 file changed, 88 insertions(+), 69 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index cfe1735..77c638c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -388,26 +388,27 @@ struct CPUMIPSState {
target_ulong CP0_CMGCRBase;
int32_t CP0_Config0;
#define CP0C0_M 31
-#define CP0C0_K23 28
-#define CP0C0_KU 25
+#define CP0C0_K23 28 /* 30..28 */
+#define CP0C0_KU 25 /* 27..25 */
#define CP0C0_MDU 20
#define CP0C0_MM 18
#define CP0C0_BM 16
+#define CP0C0_Impl 16 /* 24..16 */
#define CP0C0_BE 15
-#define CP0C0_AT 13
-#define CP0C0_AR 10
-#define CP0C0_MT 7
+#define CP0C0_AT 13 /* 14..13 */
+#define CP0C0_AR 10 /* 12..10 */
+#define CP0C0_MT 7 /* 9..7 */
#define CP0C0_VI 3
-#define CP0C0_K0 0
+#define CP0C0_K0 0 /* 2..0 */
int32_t CP0_Config1;
#define CP0C1_M 31
-#define CP0C1_MMU 25
-#define CP0C1_IS 22
-#define CP0C1_IL 19
-#define CP0C1_IA 16
-#define CP0C1_DS 13
-#define CP0C1_DL 10
-#define CP0C1_DA 7
+#define CP0C1_MMU 25 /* 30..25 */
+#define CP0C1_IS 22 /* 24..22 */
+#define CP0C1_IL 19 /* 21..19 */
+#define CP0C1_IA 16 /* 18..16 */
+#define CP0C1_DS 13 /* 15..13 */
+#define CP0C1_DL 10 /* 12..10 */
+#define CP0C1_DA 7 /* 9..7 */
#define CP0C1_C2 6
#define CP0C1_MD 5
#define CP0C1_PC 4
@@ -417,67 +418,85 @@ struct CPUMIPSState {
#define CP0C1_FP 0
int32_t CP0_Config2;
#define CP0C2_M 31
-#define CP0C2_TU 28
-#define CP0C2_TS 24
-#define CP0C2_TL 20
-#define CP0C2_TA 16
-#define CP0C2_SU 12
-#define CP0C2_SS 8
-#define CP0C2_SL 4
-#define CP0C2_SA 0
+#define CP0C2_TU 28 /* 30..28 */
+#define CP0C2_TS 24 /* 27..24 */
+#define CP0C2_TL 20 /* 23..20 */
+#define CP0C2_TA 16 /* 19..16 */
+#define CP0C2_SU 12 /* 15..12 */
+#define CP0C2_SS 8 /* 11..8 */
+#define CP0C2_SL 4 /* 7..4 */
+#define CP0C2_SA 0 /* 3..0 */
int32_t CP0_Config3;
-#define CP0C3_M 31
-#define CP0C3_BPG 30
-#define CP0C3_CMGCR 29
-#define CP0C3_MSAP 28
-#define CP0C3_BP 27
-#define CP0C3_BI 26
-#define CP0C3_SC 25
-#define CP0C3_IPLW 21
-#define CP0C3_MMAR 18
-#define CP0C3_MCU 17
-#define CP0C3_ISA_ON_EXC 16
-#define CP0C3_ISA 14
-#define CP0C3_ULRI 13
-#define CP0C3_RXI 12
-#define CP0C3_DSP2P 11
-#define CP0C3_DSPP 10
-#define CP0C3_LPA 7
-#define CP0C3_VEIC 6
-#define CP0C3_VInt 5
-#define CP0C3_SP 4
-#define CP0C3_CDMM 3
-#define CP0C3_MT 2
-#define CP0C3_SM 1
-#define CP0C3_TL 0
+#define CP0C3_M 31
+#define CP0C3_BPG 30
+#define CP0C3_CMGCR 29
+#define CP0C3_MSAP 28
+#define CP0C3_BP 27
+#define CP0C3_BI 26
+#define CP0C3_SC 25
+#define CP0C3_PW 24
+#define CP0C3_VZ 23
+#define CP0C3_IPLV 21 /* 22..21 */
+#define CP0C3_MMAR 18 /* 20..18 */
+#define CP0C3_MCU 17
+#define CP0C3_ISA_ON_EXC 16
+#define CP0C3_ISA 14 /* 15..14 */
+#define CP0C3_ULRI 13
+#define CP0C3_RXI 12
+#define CP0C3_DSP2P 11
+#define CP0C3_DSPP 10
+#define CP0C3_CTXTC 9
+#define CP0C3_ITL 8
+#define CP0C3_LPA 7
+#define CP0C3_VEIC 6
+#define CP0C3_VInt 5
+#define CP0C3_SP 4
+#define CP0C3_CDMM 3
+#define CP0C3_MT 2
+#define CP0C3_SM 1
+#define CP0C3_TL 0
int32_t CP0_Config4;
int32_t CP0_Config4_rw_bitmask;
-#define CP0C4_M 31
-#define CP0C4_IE 29
-#define CP0C4_AE 28
-#define CP0C4_KScrExist 16
-#define CP0C4_MMUExtDef 14
-#define CP0C4_FTLBPageSize 8
-#define CP0C4_FTLBWays 4
-#define CP0C4_FTLBSets 0
-#define CP0C4_MMUSizeExt 0
+#define CP0C4_M 31
+#define CP0C4_IE 29 /* 30..29 */
+#define CP0C4_AE 28
+#define CP0C4_VTLBSizeExt 24 /* 27..24 */
+#define CP0C4_KScrExist 16
+#define CP0C4_MMUExtDef 14
+#define CP0C4_FTLBPageSize 8 /* 12..8 */
+/* bit layout if MMUExtDef=1 */
+#define CP0C4_MMUSizeExt 0 /* 7..0 */
+/* bit layout if MMUExtDef=2 */
+#define CP0C4_FTLBWays 4 /* 7..4 */
+#define CP0C4_FTLBSets 0 /* 3..0 */
int32_t CP0_Config5;
int32_t CP0_Config5_rw_bitmask;
-#define CP0C5_M 31
-#define CP0C5_K 30
-#define CP0C5_CV 29
-#define CP0C5_EVA 28
-#define CP0C5_MSAEn 27
-#define CP0C5_XNP 13
-#define CP0C5_UFE 9
-#define CP0C5_FRE 8
-#define CP0C5_VP 7
-#define CP0C5_SBRI 6
-#define CP0C5_MVH 5
-#define CP0C5_LLB 4
-#define CP0C5_MRP 3
-#define CP0C5_UFR 2
-#define CP0C5_NFExists 0
+#define CP0C5_M 31
+#define CP0C5_K 30
+#define CP0C5_CV 29
+#define CP0C5_EVA 28
+#define CP0C5_MSAEn 27
+#define CP0C5_PMJ 23 /* 25..23 */
+#define CP0C5_WR2 22
+#define CP0C5_NMS 21
+#define CP0C5_ULS 20
+#define CP0C5_XPA 19
+#define CP0C5_CRCP 18
+#define CP0C5_MI 17
+#define CP0C5_GI 15 /* 16..15 */
+#define CP0C5_CA2 14
+#define CP0C5_XNP 13
+#define CP0C5_DEC 11
+#define CP0C5_L2C 10
+#define CP0C5_UFE 9
+#define CP0C5_FRE 8
+#define CP0C5_VP 7
+#define CP0C5_SBRI 6
+#define CP0C5_MVH 5
+#define CP0C5_LLB 4
+#define CP0C5_MRP 3
+#define CP0C5_UFR 2
+#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config7;
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 07/19] target/mips: Add CP0 BadInstrX register
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (5 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 06/19] target/mips: Update some CP0 registers bit definitions Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 08/19] target/mips: Add support for availability control via bit XNP Aleksandar Markovic
` (12 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Stefan Markovic <smarkovic@wavecomp.com>
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
target/mips/translate.c | 22 +++++++++++++++++++++-
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 77c638c..009202c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -323,6 +323,7 @@ struct CPUMIPSState {
target_ulong CP0_BadVAddr;
uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP;
+ uint32_t CP0_BadInstrX;
int32_t CP0_Count;
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 20100d5..5ba78ac 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 10,
- .minimum_version_id = 10,
+ .version_id = 11,
+ .minimum_version_id = 11,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2b70d1b..ae3aaab 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5328,7 +5328,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
- default:
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+ tcg_gen_andi_tl(arg, arg, ~0xffff);
+ rn = "BadInstrX";
+ break;
+ default:
goto cp0_unimplemented;
}
break;
@@ -6019,6 +6025,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6724,6 +6734,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+ tcg_gen_andi_tl(arg, arg, ~0xffff);
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7398,6 +7414,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 08/19] target/mips: Add support for availability control via bit XNP
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (6 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 07/19] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 09/19] target/mips: Add support for availability control via bit MT Aleksandar Markovic
` (11 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add a field in hflags for XNP bit, and a function check_xnp().
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/cpu.h | 3 ++-
target/mips/internal.h | 5 ++++-
target/mips/translate.c | 12 ++++++++++++
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 009202c..02ea91e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -554,7 +554,7 @@ struct CPUMIPSState {
#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
-#define MIPS_HFLAG_TMASK 0x1F5807FF
+#define MIPS_HFLAG_TMASK 0x3F5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
/* The KSU flags must be the lowest bits in hflags. The flag order
must be the same as defined for CP0 Status. This allows to use
@@ -605,6 +605,7 @@ struct CPUMIPSState {
#define MIPS_HFLAG_ELPA 0x4000000
#define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
#define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
+#define MIPS_HFLAG_XNP 0x20000000
target_ulong btarget; /* Jump / branch target */
target_ulong bcond; /* Branch condition (if needed) */
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f..97485da 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env)
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
- MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
+ MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL | MIPS_HFLAG_XNP);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->hflags |= MIPS_HFLAG_ERL;
}
@@ -402,6 +402,9 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_ELPA;
}
}
+ if (env->CP0_Config5 & (1 << CP0C5_XNP)) {
+ env->hflags |= MIPS_HFLAG_XNP;
+ }
}
void cpu_mips_tlb_flush(CPUMIPSState *env);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ae3aaab..35342e2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1902,6 +1902,18 @@ static inline void check_mvh(DisasContext *ctx)
}
#endif
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 XNP bit is set.
+ */
+static inline void check_xnp(DisasContext *ctx)
+{
+ if (unlikely(ctx->hflags & MIPS_HFLAG_XNP)) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
+
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
all callers for gen_load_fpr32 when we need the CTX parameter for
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 09/19] target/mips: Add support for availability control via bit MT
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (7 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 08/19] target/mips: Add support for availability control via bit XNP Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 10/19] target/mips: Fix MT ASE instructions' availability control Aleksandar Markovic
` (10 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add a field in hflags for MT bit, and functions check_mt() and
check_cp0_mt().
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/cpu.h | 3 ++-
target/mips/internal.h | 6 +++++-
target/mips/translate.c | 29 +++++++++++++++++++++++++++++
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 02ea91e..8a8782b 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -554,7 +554,7 @@ struct CPUMIPSState {
#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
-#define MIPS_HFLAG_TMASK 0x3F5807FF
+#define MIPS_HFLAG_TMASK 0x7F5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
/* The KSU flags must be the lowest bits in hflags. The flag order
must be the same as defined for CP0 Status. This allows to use
@@ -606,6 +606,7 @@ struct CPUMIPSState {
#define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
#define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
#define MIPS_HFLAG_XNP 0x20000000
+#define MIPS_HFLAG_MT 0x40000000
target_ulong btarget; /* Jump / branch target */
target_ulong bcond; /* Branch condition (if needed) */
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 97485da..c0e447b 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -308,7 +308,8 @@ static inline void compute_hflags(CPUMIPSState *env)
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
- MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL | MIPS_HFLAG_XNP);
+ MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL | MIPS_HFLAG_XNP |
+ MIPS_HFLAG_MT);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->hflags |= MIPS_HFLAG_ERL;
}
@@ -405,6 +406,9 @@ static inline void compute_hflags(CPUMIPSState *env)
if (env->CP0_Config5 & (1 << CP0C5_XNP)) {
env->hflags |= MIPS_HFLAG_XNP;
}
+ if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ env->hflags |= MIPS_HFLAG_MT;
+ }
}
void cpu_mips_tlb_flush(CPUMIPSState *env);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 35342e2..d827d3b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1913,6 +1913,35 @@ static inline void check_xnp(DisasContext *ctx)
}
}
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 MT bit is NOT set.
+ */
+static inline void check_mt(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_MT))) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
+/*
+ * This code generates a "coprocessor unusable" exception if CP0 is not
+ * available, and, if that is not the case, generates a "reserved instruction"
+ * exception if the Config5 MT bit is NOT set. This is needed for availability
+ * control of some of MT ASE instructions.
+ */
+static inline void check_cp0_mt(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
+ generate_exception_err(ctx, EXCP_CpU, 0);
+ } else {
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_MT))) {
+ generate_exception_err(ctx, EXCP_RI, 0);
+ }
+ }
+}
+
+
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 10/19] target/mips: Fix MT ASE instructions' availability control
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (8 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 09/19] target/mips: Add support for availability control via bit MT Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 11/19] target/mips: Implement CP0 Config1.WR bit functionality Aleksandar Markovic
` (9 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d827d3b..e62ea96 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -8393,7 +8393,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
opn = "mthc0";
break;
case OPC_MFTR:
- check_insn(ctx, ASE_MT);
+ check_cp0_enabled(ctx);
if (rd == 0) {
/* Treat as NOP. */
return;
@@ -8403,7 +8403,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
opn = "mftr";
break;
case OPC_MTTR:
- check_insn(ctx, ASE_MT);
+ check_cp0_enabled(ctx);
gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
opn = "mttr";
@@ -18619,7 +18619,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
break;
case OPC_FORK:
- check_insn(ctx, ASE_MT);
+ check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -18632,7 +18632,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_YIELD:
- check_insn(ctx, ASE_MT);
+ check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
@@ -19929,22 +19929,22 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_dmt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_EMT:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_emt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_DVPE:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 11/19] target/mips: Implement CP0 Config1.WR bit functionality
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (9 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 10/19] target/mips: Fix MT ASE instructions' availability control Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 12/19] target/mips: Don't update BadVAddr register in Debug Mode Aleksandar Markovic
` (8 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Stefan Markovic <smarkovic@wavecomp.com>
Add testing Config1.WR bit into watch exception handling logic.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e62ea96..6f4bdc9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5562,6 +5562,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5579,6 +5580,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6261,6 +6263,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6278,6 +6281,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6964,6 +6968,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6981,6 +6986,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7645,6 +7651,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7662,6 +7669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 12/19] target/mips: Don't update BadVAddr register in Debug Mode
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (10 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 11/19] target/mips: Implement CP0 Config1.WR bit functionality Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 13/19] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 Aleksandar Markovic
` (7 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Yongbok Kim <yongbok.kim@mips.com>
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.c | 4 +++-
target/mips/op_helper.c | 12 +++++++++---
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 8cf91ce..e215af9 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -502,7 +502,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
break;
}
/* Raise exception */
- env->CP0_BadVAddr = address;
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = address;
+ }
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 41d3634..0b2663b 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -271,7 +271,9 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
if (arg & almask) { \
- env->CP0_BadVAddr = arg; \
+ if (!(env->hflags & MIPS_HFLAG_DM)) { \
+ env->CP0_BadVAddr = arg; \
+ } \
do_raise_exception(env, EXCP_AdEL, GETPC()); \
} \
env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
@@ -291,7 +293,9 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
target_long tmp; \
\
if (arg2 & almask) { \
- env->CP0_BadVAddr = arg2; \
+ if (!(env->hflags & MIPS_HFLAG_DM)) { \
+ env->CP0_BadVAddr = arg2; \
+ } \
do_raise_exception(env, EXCP_AdES, GETPC()); \
} \
if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
@@ -2437,7 +2441,9 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
int error_code = 0;
int excp;
- env->CP0_BadVAddr = addr;
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = addr;
+ }
if (access_type == MMU_DATA_STORE) {
excp = EXCP_AdES;
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 13/19] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (11 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 12/19] target/mips: Don't update BadVAddr register in Debug Mode Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 14/19] target/mips: Add gen_op_addr_addi() Aleksandar Markovic
` (6 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Yongbok Kim <yongbok.kim@mips.com>
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6f4bdc9..420f1df 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4938,12 +4938,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4954,6 +4953,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -5006,12 +5006,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -5023,6 +5022,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 14/19] target/mips: Add gen_op_addr_addi()
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (12 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 13/19] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 15/19] elf: Remove duplicate preprocessor constant definition Aleksandar Markovic
` (5 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Stefan Markovic <smarkovic@wavecomp.com>
Add gen_op_addr_addi(). This function will be used in emulation of
some nanoMIPS instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 420f1df..d67e747 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1746,6 +1746,18 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv
#endif
}
+static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
+ target_long ofs)
+{
+ tcg_gen_addi_tl(ret, base, ofs);
+
+#if defined(TARGET_MIPS64)
+ if (ctx->hflags & MIPS_HFLAG_AWRAP) {
+ tcg_gen_ext32s_i64(ret, ret);
+ }
+#endif
+}
+
/* Addresses computation (translation time) */
static target_long addr_add(DisasContext *ctx, target_long base,
target_long offset)
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 15/19] elf: Remove duplicate preprocessor constant definition
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (13 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 14/19] target/mips: Add gen_op_addr_addi() Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 16/19] elf: Add ELF flags for MIPS machine variants Aleksandar Markovic
` (4 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH.
The duplicate was introduced in commit 45506bdd. It placed the
constant EF_MIPS_ARCH in a better place, however it did not remove
the original. This patch removes the original occurrence.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index 934dbbd..60f6cbe 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -61,7 +61,6 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_FP64 0x00000200
#define EF_MIPS_NAN2008 0x00000400
-#define EF_MIPS_ARCH 0xf0000000
/* These constants define the different elf file types */
#define ET_NONE 0
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 16/19] elf: Add ELF flags for MIPS machine variants
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (14 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 15/19] elf: Remove duplicate preprocessor constant definition Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 17/19] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers Aleksandar Markovic
` (3 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add MIPS machine variants ELF flags so that the emulation behavior
can be adjusted if needed.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
include/elf.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 60f6cbe..28a5a63 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -62,6 +62,29 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_FP64 0x00000200
#define EF_MIPS_NAN2008 0x00000400
+/* MIPS machine variant */
+#define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */
+#define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */
+#define EF_MIPS_MACH_4010 0x00820000 /* LSI R4010 */
+#define EF_MIPS_MACH_4100 0x00830000 /* NEC VR4100 */
+#define EF_MIPS_MACH_4650 0x00850000 /* MIPS R4650 */
+#define EF_MIPS_MACH_4120 0x00870000 /* NEC VR4120 */
+#define EF_MIPS_MACH_4111 0x00880000 /* NEC VR4111/VR4181 */
+#define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
+#define EF_MIPS_MACH_OCTEON 0x008b0000 /* Cavium Networks Octeon */
+#define EF_MIPS_MACH_XLR 0x008c0000 /* RMI Xlr */
+#define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */
+#define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */
+#define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */
+#define EF_MIPS_MACH_5900 0x00920000 /* MIPS R5900 */
+#define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */
+#define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra's RM9000 */
+#define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */
+#define EF_MIPS_MACH_LS2F 0x00a10000 /* ST Microelectronics Loongson 2F */
+#define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
+#define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
+
+
/* These constants define the different elf file types */
#define ET_NONE 0
#define ET_REL 1
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 17/19] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (15 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 16/19] elf: Add ELF flags for MIPS machine variants Aleksandar Markovic
@ 2018-08-14 18:16 ` Aleksandar Markovic
2018-08-14 18:17 ` [Qemu-devel] [PULL 18/19] linux-user: Add preprocessor availability control to some syscalls Aleksandar Markovic
` (2 subsequent siblings)
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:16 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Synchronize content of linux-user/mips/syscall_nr.h and
linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers.
This adds 9 new syscall numbers, the last being NR_io_pgetevents.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/mips/syscall_nr.h | 9 +++++++++
linux-user/mips64/syscall_nr.h | 18 ++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/linux-user/mips/syscall_nr.h b/linux-user/mips/syscall_nr.h
index ced3280..e70adfc 100644
--- a/linux-user/mips/syscall_nr.h
+++ b/linux-user/mips/syscall_nr.h
@@ -363,3 +363,12 @@
#define TARGET_NR_userfaultfd (TARGET_NR_Linux + 357)
#define TARGET_NR_membarrier (TARGET_NR_Linux + 358)
#define TARGET_NR_mlock2 (TARGET_NR_Linux + 359)
+#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 360)
+#define TARGET_NR_preadv2 (TARGET_NR_Linux + 361)
+#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 362)
+#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 363)
+#define TARGET_NR_pkey_alloc (TARGET_NR_Linux + 364)
+#define TARGET_NR_pkey_free (TARGET_NR_Linux + 365)
+#define TARGET_NR_statx (TARGET_NR_Linux + 366)
+#define TARGET_NR_rseq (TARGET_NR_Linux + 367)
+#define TARGET_NR_io_pgetevents (TARGET_NR_Linux + 368)
diff --git a/linux-user/mips64/syscall_nr.h b/linux-user/mips64/syscall_nr.h
index 746cc26..ff218a9 100644
--- a/linux-user/mips64/syscall_nr.h
+++ b/linux-user/mips64/syscall_nr.h
@@ -327,6 +327,15 @@
#define TARGET_NR_userfaultfd (TARGET_NR_Linux + 321)
#define TARGET_NR_membarrier (TARGET_NR_Linux + 322)
#define TARGET_NR_mlock2 (TARGET_NR_Linux + 323)
+#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 324)
+#define TARGET_NR_preadv2 (TARGET_NR_Linux + 325)
+#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 326)
+#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 327)
+#define TARGET_NR_pkey_alloc (TARGET_NR_Linux + 328)
+#define TARGET_NR_pkey_free (TARGET_NR_Linux + 329)
+#define TARGET_NR_statx (TARGET_NR_Linux + 330)
+#define TARGET_NR_rseq (TARGET_NR_Linux + 331)
+#define TARGET_NR_io_pgetevents (TARGET_NR_Linux + 332)
#else
/*
@@ -653,4 +662,13 @@
#define TARGET_NR_userfaultfd (TARGET_NR_Linux + 317)
#define TARGET_NR_membarrier (TARGET_NR_Linux + 318)
#define TARGET_NR_mlock2 (TARGET_NR_Linux + 319)
+#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 320)
+#define TARGET_NR_preadv2 (TARGET_NR_Linux + 321)
+#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 322)
+#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 323)
+#define TARGET_NR_pkey_alloc (TARGET_NR_Linux + 324)
+#define TARGET_NR_pkey_free (TARGET_NR_Linux + 325)
+#define TARGET_NR_statx (TARGET_NR_Linux + 326)
+#define TARGET_NR_rseq (TARGET_NR_Linux + 327)
+#define TARGET_NR_io_pgetevents (TARGET_NR_Linux + 328)
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 18/19] linux-user: Add preprocessor availability control to some syscalls
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (16 preceding siblings ...)
2018-08-14 18:16 ` [Qemu-devel] [PULL 17/19] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers Aleksandar Markovic
@ 2018-08-14 18:17 ` Aleksandar Markovic
2018-08-14 18:17 ` [Qemu-devel] [PULL 19/19] qemu-doc: Amend MIPS-related items Aleksandar Markovic
2018-08-15 19:20 ` [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Peter Maydell
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Rikalo <arikalo@wavecomp.com>
Add ability to target platforms to individually include user-mode
support for system calls from "stat" group of system calls.
This change is related to new nanoMIPS platform in the sense that
it supports a different set of "stat" system calls than any other
target. nanoMIPS does not support structures stat and stat64 at
all. Also, support for certain number of other system calls is
dropped in nanoMIPS (those are most of the time obsoleted system
calls).
Without this patch, build for nanoMIPS would fail.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
linux-user/strace.c | 14 +++++++++++++-
linux-user/syscall.c | 29 +++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index bd897a3..33f4a50 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -2304,7 +2304,19 @@ print_statfs(const struct syscallname *name,
print_pointer(arg1, 1);
print_syscall_epilogue(name);
}
-#define print_statfs64 print_statfs
+#endif
+
+#ifdef TARGET_NR_statfs64
+static void
+print_statfs64(const struct syscallname *name,
+ abi_long arg0, abi_long arg1, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5)
+{
+ print_syscall_prologue(name);
+ print_string(arg0, 0);
+ print_pointer(arg1, 1);
+ print_syscall_epilogue(name);
+}
#endif
#ifdef TARGET_NR_symlink
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index dfc851c..3d57966 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -7286,6 +7286,9 @@ static inline int target_to_host_mlockall_arg(int arg)
}
#endif
+#if (defined(TARGET_NR_stat64) || defined(TARGET_NR_lstat64) || \
+ defined(TARGET_NR_fstat64) || defined(TARGET_NR_fstatat64) || \
+ defined(TARGET_NR_newfstatat))
static inline abi_long host_to_target_stat64(void *cpu_env,
abi_ulong target_addr,
struct stat *host_st)
@@ -7348,6 +7351,7 @@ static inline abi_long host_to_target_stat64(void *cpu_env,
return 0;
}
+#endif
/* ??? Using host futex calls even when target atomic operations
are not really atomic probably breaks things. However implementing
@@ -7996,8 +8000,15 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
{
CPUState *cpu = ENV_GET_CPU(cpu_env);
abi_long ret;
+#if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \
+ || defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \
+ || defined(TARGET_NR_fstat) || defined(TARGET_NR_fstat64)
struct stat st;
+#endif
+#if defined(TARGET_NR_statfs) || defined(TARGET_NR_statfs64) \
+ || defined(TARGET_NR_fstatfs)
struct statfs stfs;
+#endif
void *p;
#if defined(DEBUG_ERESTARTSYS)
@@ -8365,9 +8376,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_oldstat:
goto unimplemented;
#endif
+#ifdef TARGET_NR_lseek
case TARGET_NR_lseek:
ret = get_errno(lseek(arg1, arg2, arg3));
break;
+#endif
#if defined(TARGET_NR_getxpid) && defined(TARGET_ALPHA)
/* Alpha specific */
case TARGET_NR_getxpid:
@@ -9251,6 +9264,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(sethostname(p, arg2));
unlock_user(p, arg1, 0);
break;
+#ifdef TARGET_NR_setrlimit
case TARGET_NR_setrlimit:
{
int resource = target_to_host_resource(arg1);
@@ -9264,6 +9278,8 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(setrlimit(resource, &rlim));
}
break;
+#endif
+#ifdef TARGET_NR_getrlimit
case TARGET_NR_getrlimit:
{
int resource = target_to_host_resource(arg1);
@@ -9280,6 +9296,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
}
break;
+#endif
case TARGET_NR_getrusage:
{
struct rusage rusage;
@@ -9644,15 +9661,19 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(munlockall());
break;
#endif
+#ifdef TARGET_NR_truncate
case TARGET_NR_truncate:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(truncate(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
+#ifdef TARGET_NR_ftruncate
case TARGET_NR_ftruncate:
ret = get_errno(ftruncate(arg1, arg2));
break;
+#endif
case TARGET_NR_fchmod:
ret = get_errno(fchmod(arg1, arg2));
break;
@@ -9688,6 +9709,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_profil:
goto unimplemented;
#endif
+#ifdef TARGET_NR_statfs
case TARGET_NR_statfs:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -9719,9 +9741,12 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user_struct(target_stfs, arg2, 1);
}
break;
+#endif
+#ifdef TARGET_NR_fstatfs
case TARGET_NR_fstatfs:
ret = get_errno(fstatfs(arg1, &stfs));
goto convert_statfs;
+#endif
#ifdef TARGET_NR_statfs64
case TARGET_NR_statfs64:
if (!(p = lock_user_string(arg1)))
@@ -9969,6 +9994,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
goto do_stat;
#endif
+#ifdef TARGET_NR_fstat
case TARGET_NR_fstat:
{
ret = get_errno(fstat(arg1, &st));
@@ -9998,6 +10024,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
}
break;
+#endif
#ifdef TARGET_NR_olduname
case TARGET_NR_olduname:
goto unimplemented;
@@ -10997,6 +11024,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
break;
#ifdef CONFIG_SENDFILE
+#ifdef TARGET_NR_sendfile
case TARGET_NR_sendfile:
{
off_t *offp = NULL;
@@ -11017,6 +11045,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
}
+#endif
#ifdef TARGET_NR_sendfile64
case TARGET_NR_sendfile64:
{
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PULL 19/19] qemu-doc: Amend MIPS-related items
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (17 preceding siblings ...)
2018-08-14 18:17 ` [Qemu-devel] [PULL 18/19] linux-user: Add preprocessor availability control to some syscalls Aleksandar Markovic
@ 2018-08-14 18:17 ` Aleksandar Markovic
2018-08-15 19:20 ` [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Peter Maydell
19 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-14 18:17 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Amend MIPS-related items in qemu-doc.texi
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
qemu-doc.texi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index abfd2db..8ea6bfa 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -2693,8 +2693,17 @@ The binary format is detected automatically.
@command{qemu-microblaze} TODO.
@cindex user mode (MIPS)
-@command{qemu-mips} TODO.
-@command{qemu-mipsel} TODO.
+@command{qemu-mips} executes 32-bit big endian MIPS binaries (MIPS O32 ABI).
+
+@command{qemu-mipsel} executes 32-bit little endian MIPS binaries (MIPS O32 ABI).
+
+@command{qemu-mips64} executes 64-bit big endian MIPS binaries (MIPS O64 ABI).
+
+@command{qemu-mips64el} executes 64-bit little endian MIPS binaries (MIPS O64 ABI).
+
+@command{qemu-mipsn32} executes 32-bit big endian MIPS binaries (MIPS N32 ABI).
+
+@command{qemu-mipsn32el} executes 32-bit little endian MIPS binaries (MIPS N32 ABI).
@cindex user mode (NiosII)
@command{qemu-nios2} TODO.
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
` (18 preceding siblings ...)
2018-08-14 18:17 ` [Qemu-devel] [PULL 19/19] qemu-doc: Amend MIPS-related items Aleksandar Markovic
@ 2018-08-15 19:20 ` Peter Maydell
2018-08-15 19:35 ` [Qemu-devel] ?==?utf-8?q? [PULL?==?utf-8?q? " Aleksandar Markovic
19 siblings, 1 reply; 23+ messages in thread
From: Peter Maydell @ 2018-08-15 19:20 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: QEMU Developers
On 14 August 2018 at 19:16, Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> The following changes since commit 38441756b70eec5807b5f60dad11a93a91199866:
>
> Update version for v3.0.0 release (2018-08-14 16:38:43 +0100)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-aug-14-2018
>
> for you to fetch changes up to 20d4e01b6486b15d1f3d9ff2d51bba2bf00ebf94:
>
> qemu-doc: Amend MIPS-related items (2018-08-14 19:59:03 +0200)
>
> ----------------------------------------------------------------
> MIPS queue for QEMU upstream, August 14, 2018
>
> This is the first part of nanoMIPS support for QEMU. It contains
> various fixes and improvements that are related to nanoMIPS support,
> or are discovered while working on nanoMIPS support. Most of them are
> fairly simple changes, but each of them has its own significance and
> importance for nanoMIPS support.
>
> The second part that contains QEMU support for core nanoMIPS
> functionality will remain under review for some time.
>
> The third part that mainly contains Linux user support will likely
> remain under review for some longer period.
>
> ----------------------------------------------------------------
Hi; this fails to build on clang:
/home/petmay01/linaro/qemu-for-merges/target/mips/translate.c:1749:20:
error: unused function 'gen_op_addr_addi' [-Werror,-Wunused-funct
ion]
static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
^
/home/petmay01/linaro/qemu-for-merges/target/mips/translate.c:1921:20:
error: unused function 'check_xnp' [-Werror,-Wunused-function]
static inline void check_xnp(DisasContext *ctx)
^
2 errors generated.
The functions do appear to be genuinely unused.
thanks
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] ?==?utf-8?q? [PULL?==?utf-8?q? 00/19] MIPS queue for QEMU upstream, August 14, 2018
2018-08-15 19:20 ` [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Peter Maydell
@ 2018-08-15 19:35 ` Aleksandar Markovic
2018-08-15 19:50 ` [Qemu-devel] [PULL " Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2018-08-15 19:35 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
These functions are used in the patches that follow in nanoMIPS series, but not submitted in this pull request.
Ok, I will reorganize the patches so that there is no such case, and will send the new pull request soon.
Do we require that bisect works for clang builds too (meaning that after each patch, clang build must be success)?
Aleksandar
-------- Original Message --------
Subject: Re: [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018
Date: Wednesday, August 15, 2018 21:20 CEST
From: Peter Maydell <peter.maydell@linaro.org>
To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
CC: QEMU Developers <qemu-devel@nongnu.org>
References: <1534270621-27332-1-git-send-email-aleksandar.markovic@rt-rk.com>
On 14 August 2018 at 19:16, Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> The following changes since commit 38441756b70eec5807b5f60dad11a93a91199866:
>
> Update version for v3.0.0 release (2018-08-14 16:38:43 +0100)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-aug-14-2018
>
> for you to fetch changes up to 20d4e01b6486b15d1f3d9ff2d51bba2bf00ebf94:
>
> qemu-doc: Amend MIPS-related items (2018-08-14 19:59:03 +0200)
>
> ----------------------------------------------------------------
> MIPS queue for QEMU upstream, August 14, 2018
>
> This is the first part of nanoMIPS support for QEMU. It contains
> various fixes and improvements that are related to nanoMIPS support,
> or are discovered while working on nanoMIPS support. Most of them are
> fairly simple changes, but each of them has its own significance and
> importance for nanoMIPS support.
>
> The second part that contains QEMU support for core nanoMIPS
> functionality will remain under review for some time.
>
> The third part that mainly contains Linux user support will likely
> remain under review for some longer period.
>
> ----------------------------------------------------------------
Hi; this fails to build on clang:
/home/petmay01/linaro/qemu-for-merges/target/mips/translate.c:1749:20:
error: unused function 'gen_op_addr_addi' [-Werror,-Wunused-funct
ion]
static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
^
/home/petmay01/linaro/qemu-for-merges/target/mips/translate.c:1921:20:
error: unused function 'check_xnp' [-Werror,-Wunused-function]
static inline void check_xnp(DisasContext *ctx)
^
2 errors generated.
The functions do appear to be genuinely unused.
thanks
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018
2018-08-15 19:35 ` [Qemu-devel] ?==?utf-8?q? [PULL?==?utf-8?q? " Aleksandar Markovic
@ 2018-08-15 19:50 ` Peter Maydell
0 siblings, 0 replies; 23+ messages in thread
From: Peter Maydell @ 2018-08-15 19:50 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: QEMU Developers
On 15 August 2018 at 20:35, Aleksandar Markovic
<Aleksandar.Markovic@rt-rk.com> wrote:
> These functions are used in the patches that follow in nanoMIPS series, but
> not submitted in this pull request.
>
> Ok, I will reorganize the patches so that there is no such case, and will
> send the new pull request soon.
>
> Do we require that bisect works for clang builds too (meaning that after
> each patch, clang build must be success)?
Yes, please. (As usual with breaking-bisection, if you get it wrong by
accident we may well not notice, but it's worth trying to get right.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-08-15 19:51 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-08-14 18:16 [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 01/19] MAINTAINERS: Update target/mips maintainer's email addresses Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 02/19] target/mips: Avoid case statements formulated by ranges - part 1 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 03/19] target/mips: Avoid case statements formulated by ranges - part 2 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 04/19] target/mips: Mark switch fallthroughs with interpretable comments Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 05/19] target/mips: Fix two instances of shadow variables Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 06/19] target/mips: Update some CP0 registers bit definitions Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 07/19] target/mips: Add CP0 BadInstrX register Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 08/19] target/mips: Add support for availability control via bit XNP Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 09/19] target/mips: Add support for availability control via bit MT Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 10/19] target/mips: Fix MT ASE instructions' availability control Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 11/19] target/mips: Implement CP0 Config1.WR bit functionality Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 12/19] target/mips: Don't update BadVAddr register in Debug Mode Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 13/19] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 14/19] target/mips: Add gen_op_addr_addi() Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 15/19] elf: Remove duplicate preprocessor constant definition Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 16/19] elf: Add ELF flags for MIPS machine variants Aleksandar Markovic
2018-08-14 18:16 ` [Qemu-devel] [PULL 17/19] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers Aleksandar Markovic
2018-08-14 18:17 ` [Qemu-devel] [PULL 18/19] linux-user: Add preprocessor availability control to some syscalls Aleksandar Markovic
2018-08-14 18:17 ` [Qemu-devel] [PULL 19/19] qemu-doc: Amend MIPS-related items Aleksandar Markovic
2018-08-15 19:20 ` [Qemu-devel] [PULL 00/19] MIPS queue for QEMU upstream, August 14, 2018 Peter Maydell
2018-08-15 19:35 ` [Qemu-devel] ?==?utf-8?q? [PULL?==?utf-8?q? " Aleksandar Markovic
2018-08-15 19:50 ` [Qemu-devel] [PULL " Peter Maydell
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