From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WtuNI-0006KA-0D for qemu-devel@nongnu.org; Mon, 09 Jun 2014 03:52:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WtuND-0005mQ-62 for qemu-devel@nongnu.org; Mon, 09 Jun 2014 03:52:11 -0400 Received: from mail-lb0-f171.google.com ([209.85.217.171]:63600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WtuNC-0005mK-UJ for qemu-devel@nongnu.org; Mon, 09 Jun 2014 03:52:07 -0400 Received: by mail-lb0-f171.google.com with SMTP id 10so2827663lbg.16 for ; Mon, 09 Jun 2014 00:52:05 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Peter Maydell Date: Mon, 9 Jun 2014 08:51:45 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Question] Qemu Register Mapping Directly in AARCH64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Chaos Shu Cc: QEMU Developers On 9 June 2014 06:59, Chaos Shu wrote: > I=E2=80=99ve noticed that Qemu maintained the target arch register in mem= ory for > capacity, but the load/store really cost a bit much, is there any way map > the register directly. Our JIT's register allocator will avoid storing the guest register value back to RAM unless it has to (eg if we might be about to fault, call a helper which would trash the host register, etc). Using a target-agnostic JIT like this is a pretty fundamental design decision that isn't easy to change. In any case the regs[] array in the CPU state struct will always be in L1 cache so access will be fast. thanks -- PMM