From: Peter Maydell <peter.maydell@linaro.org>
To: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Cc: qemu-devel@nongnu.org, "Laurent Vivier" <lvivier@redhat.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
qemu-arm@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Thomas Huth" <thuth@redhat.com>,
"Inès Varhol" <ines.varhol@telecom-paris.fr>,
"Samuel Tardieu" <samuel.tardieu@telecom-paris.fr>
Subject: Re: [PATCH v2 0/6] hw/char: Implement the STM32L4x5 USART, UART and LPUART
Date: Thu, 28 Mar 2024 16:10:24 +0000 [thread overview]
Message-ID: <CAFEAcA-h-ddfyNXaa_swFJVc61cDbR9tg34AC88nqZLgfbzCsw@mail.gmail.com> (raw)
In-Reply-To: <20240324165545.201908-1-arnaud.minier@telecom-paris.fr>
On Sun, 24 Mar 2024 at 16:56, Arnaud Minier
<arnaud.minier@telecom-paris.fr> wrote:
>
> This patch adds the STM32L4x5 USART
> (Universal Synchronous/Asynchronous Receiver/Transmitter)
> device and is part of a series implementing the
> STM32L4x5 with a few peripherals.
>
> It implements the necessary functionalities to receive/send
> characters over the serial port, which are useful to
> communicate with the program currently running.
>
> Many thanks Peter for your review, I think I addressed almost
> everything.
> I'm just unsure about how to handle the waiting time in the tests.
> I understand your concerns about the unreliability of using the wallclock
> time but I don't understand how using clock_step() would make it
> more reliable. We will always be waiting on something
> that is out of our control (i.e. the OS).
> I increased the delay from 5s to 10min to match the microbit test
> and added a comment (I paraphrased your comment, is that okay ?).
I think I was slightly confused between two things. For
a lot of qtests we do want to use clock_step() and not
have wallclock-based delays, but we can only do that where
the thing we're waiting for is purely simulation time
(i.e. where we triggered a change via a qtest write and
then want to look for the result via a qtest read).
Where we're triggering something via a different OS
pathway (e.g. here where we write to the socket that's
backing the chardev connected to the UART and then look
at the UART registers) we do need a wallclock delay.
I recommend you follow Thomas's suggestions about timeouts
in his comments on patch 6; I'd forgotten we have a
meson timeout now too.
thanks
-- PMM
prev parent reply other threads:[~2024-03-28 16:11 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-24 16:55 [PATCH v2 0/6] hw/char: Implement the STM32L4x5 USART, UART and LPUART Arnaud Minier
2024-03-24 16:55 ` [PATCH v2 1/6] hw/misc/stm32l4x5_rcc: Propagate period when enabling a clock Arnaud Minier
2024-03-24 16:55 ` [PATCH v2 2/6] hw/char: Implement STM32L4x5 USART skeleton Arnaud Minier
2024-03-28 15:55 ` Peter Maydell
2024-03-24 16:55 ` [PATCH v2 3/6] hw/char/stm32l4x5_usart: Enable serial read and write Arnaud Minier
2024-03-28 15:59 ` Peter Maydell
2024-03-24 16:55 ` [PATCH v2 4/6] hw/char/stm32l4x5_usart: Add options for serial parameters setting Arnaud Minier
2024-03-28 16:03 ` Peter Maydell
2024-03-24 16:55 ` [PATCH v2 5/6] hw/arm: Add the USART to the stm32l4x5 SoC Arnaud Minier
2024-03-28 16:06 ` Peter Maydell
2024-03-24 16:55 ` [PATCH v2 6/6] tests/qtest: Add tests for the STM32L4x5 USART Arnaud Minier
2024-03-25 6:19 ` Thomas Huth
2024-03-28 16:14 ` Peter Maydell
2024-03-28 16:10 ` Peter Maydell [this message]
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