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From: Peter Maydell <peter.maydell@linaro.org>
To: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Rob Herring <rob.herring@linaro.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
Subject: Re: [Qemu-devel] [PATCH] hw/intc/arm_gic: Fix GIC_SET_LEVEL
Date: Mon, 24 Feb 2014 15:36:48 +0000	[thread overview]
Message-ID: <CAFEAcA-h6Jw1g5TTLJEu5M9Z_JB_59yMRwJsV2LbqqGy=6b6DA@mail.gmail.com> (raw)
In-Reply-To: <CAMJs5B8UVh3wPkGFWgtAQF9uKVeC_0dCXFouzF842p9aL8B9=Q@mail.gmail.com>

On 23 February 2014 16:32, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> On 21 February 2014 17:03, Christoffer Dall <christoffer.dall@linaro.org> wrote:
>> The GIC_SET_LEVEL macro unfortunately overwrote the entire level
>> bitmask instead of just or'ing on the necessary bits, causing active
>> level PPIs on a core to clear PPIs on other cores.
>>
>> I introduced this bug, sorry about that.
>>
> Actually it turns out this was ancient, I was a little too quick to
> blame myself there.

Yes, it's been present since 2007 or so. Probably not noticed
at that time because all the 11MPcore PPIs are edge rather than
level triggered.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

I'll remove the line about it being your fault when I apply
this to target-arm.next :-)

thanks
-- PMM

      reply	other threads:[~2014-02-24 15:37 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-22  1:03 [Qemu-devel] [PATCH] hw/intc/arm_gic: Fix GIC_SET_LEVEL Christoffer Dall
2014-02-23 16:32 ` Christoffer Dall
2014-02-24 15:36   ` Peter Maydell [this message]

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