From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47500) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WHxal-0007Zn-D8 for qemu-devel@nongnu.org; Mon, 24 Feb 2014 10:37:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WHxag-0003pf-Jo for qemu-devel@nongnu.org; Mon, 24 Feb 2014 10:37:15 -0500 Received: from mail-la0-f47.google.com ([209.85.215.47]:62719) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WHxag-0003pT-D2 for qemu-devel@nongnu.org; Mon, 24 Feb 2014 10:37:10 -0500 Received: by mail-la0-f47.google.com with SMTP id y1so1550294lam.34 for ; Mon, 24 Feb 2014 07:37:09 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1393031030-8692-1-git-send-email-christoffer.dall@linaro.org> From: Peter Maydell Date: Mon, 24 Feb 2014 15:36:48 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH] hw/intc/arm_gic: Fix GIC_SET_LEVEL List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Christoffer Dall Cc: Rob Herring , QEMU Developers , "kvmarm@lists.cs.columbia.edu" On 23 February 2014 16:32, Christoffer Dall wrote: > On 21 February 2014 17:03, Christoffer Dall wrote: >> The GIC_SET_LEVEL macro unfortunately overwrote the entire level >> bitmask instead of just or'ing on the necessary bits, causing active >> level PPIs on a core to clear PPIs on other cores. >> >> I introduced this bug, sorry about that. >> > Actually it turns out this was ancient, I was a little too quick to > blame myself there. Yes, it's been present since 2007 or so. Probably not noticed at that time because all the 11MPcore PPIs are edge rather than level triggered. Reviewed-by: Peter Maydell I'll remove the line about it being your fault when I apply this to target-arm.next :-) thanks -- PMM