From: Peter Maydell <peter.maydell@linaro.org>
To: Shannon Zhao <shannon.zhao@linaro.org>
Cc: Sergey Fedorov <serge.fdrv@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] target-arm: fix REVIDR reset value
Date: Tue, 2 Jun 2015 14:18:46 +0100 [thread overview]
Message-ID: <CAFEAcA-hgDffmBSbrw3_4jVx=3bcngb-sseoZcFj2SW5VX4duQ@mail.gmail.com> (raw)
In-Reply-To: <556DA6CC.6040802@linaro.org>
On 2 June 2015 at 13:51, Shannon Zhao <shannon.zhao@linaro.org> wrote:
> Hi,
>
> On 2015/6/2 20:21, Sergey Fedorov wrote:
>> According to ARM Cortex-A57 TRM, REVIDR reset value should be zero. So
>> let REVIDR reset value be specified by CPU model and fix it for
>> Cortex-A57.
>>
>
> Also need to fix it for Cortex-A53?
Yes, please.
Also you need to update the comment:
/* v8 MIDR -- the wildcard isn't necessary, and nor is the
* variable-MIDR TI925 behaviour. Instead we have a single
* (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
*/
since the REVIDR isn't an alias of the MIDR any more.
NB: a bug that's been on my todo list for ages is that the comment
is incorrect about the wildcard being unnecessary -- this was a
misreading of the ARM ARM by me when I wrote that code. v8 *does*
retain the aliases of the MIDR at any unoccupied opc2 values
in the 0, c0, c0, x space, and we should provide the wildcard
encoding here.
thanks
-- PMM
next prev parent reply other threads:[~2015-06-02 13:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-02 12:21 [Qemu-devel] [PATCH] target-arm: fix REVIDR reset value Sergey Fedorov
2015-06-02 12:51 ` Shannon Zhao
2015-06-02 13:18 ` Peter Maydell [this message]
2015-06-02 13:28 ` Peter Maydell
2015-06-03 7:40 ` Sergey Fedorov
2015-06-02 13:54 ` Peter Maydell
2015-06-03 7:42 ` Sergey Fedorov
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