From: Peter Maydell <peter.maydell@linaro.org>
To: Greg Bellows <greg.bellows@linaro.org>
Cc: Sergey Fedorov <serge.fdrv@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v10 06/26] target-arm: add secure state bit to CPREG hash
Date: Mon, 17 Nov 2014 14:59:28 +0000 [thread overview]
Message-ID: <CAFEAcA-jBAq5GMGr9RvRe5PZSfA5rR1X23rnWRgt2nf=GDQefQ@mail.gmail.com> (raw)
In-Reply-To: <1415289073-14681-7-git-send-email-greg.bellows@linaro.org>
On 6 November 2014 15:50, Greg Bellows <greg.bellows@linaro.org> wrote:
> Added additional NS-bit to CPREG hash encoding. Updated hash lookup
> locations to specify hash bit currently set to non-secure.
>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
next prev parent reply other threads:[~2014-11-17 14:59 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-06 15:50 [Qemu-devel] [PATCH v10 00/26] target-arm: add Security Extensions for CPUs Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 01/26] target-arm: extend async excp masking Greg Bellows
2014-11-17 14:46 ` Peter Maydell
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 02/26] target-arm: add async excp target_el function Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 03/26] target-arm: add banked register accessors Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 04/26] target-arm: add non-secure Translation Block flag Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 05/26] target-arm: add CPREG secure state support Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 06/26] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-11-17 14:59 ` Peter Maydell [this message]
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-11-17 15:00 ` Peter Maydell
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 08/26] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 10/26] target-arm: add NSACR register Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 11/26] target-arm: add SDER definition Greg Bellows
2014-11-06 15:50 ` [Qemu-devel] [PATCH v10 12/26] target-arm: add MVBAR support Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-11-17 15:13 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-11-17 15:10 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 15/26] target-arm: make CSSELR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 16/26] target-arm: make TTBR0/1 banked Greg Bellows
2014-11-17 15:22 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 17/26] target-arm: make TTBCR banked Greg Bellows
2014-11-17 15:34 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 18/26] target-arm: make DACR banked Greg Bellows
2014-11-17 15:19 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 19/26] target-arm: make IFSR banked Greg Bellows
2014-11-17 15:16 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 20/26] target-arm: make DFSR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 21/26] target-arm: make IFAR/DFAR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 22/26] target-arm: make PAR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 23/26] target-arm: make VBAR banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 24/26] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-11-17 15:25 ` Peter Maydell
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 25/26] target-arm: make MAIR0/1 banked Greg Bellows
2014-11-06 15:51 ` [Qemu-devel] [PATCH v10 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAFEAcA-jBAq5GMGr9RvRe5PZSfA5rR1X23rnWRgt2nf=GDQefQ@mail.gmail.com' \
--to=peter.maydell@linaro.org \
--cc=aggelerf@ethz.ch \
--cc=edgar.iglesias@gmail.com \
--cc=greg.bellows@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=serge.fdrv@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).