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Thu, 22 Sep 2022 07:08:04 -0700 (PDT) MIME-Version: 1.0 References: <20220906100528.343244-1-richard.henderson@linaro.org> <20220906100528.343244-10-richard.henderson@linaro.org> In-Reply-To: <20220906100528.343244-10-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 22 Sep 2022 15:07:53 +0100 Message-ID: Subject: Re: [PATCH v4 9/9] target/arm: Enable TARGET_TB_PCREL To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 6 Sept 2022 at 11:31, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/cpu-param.h | 2 ++ > target/arm/translate.h | 6 ++++ > target/arm/cpu.c | 23 +++++++------- > target/arm/translate-a64.c | 37 ++++++++++++++++++----- > target/arm/translate.c | 62 ++++++++++++++++++++++++++++++-------- > 5 files changed, 100 insertions(+), 30 deletions(-) > > diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h > index 68ffb12427..ef62371d8f 100644 > --- a/target/arm/cpu-param.h > +++ b/target/arm/cpu-param.h > @@ -34,4 +34,6 @@ > > #define NB_MMU_MODES 15 > > +#define TARGET_TB_PCREL 1 > + > #endif > diff --git a/target/arm/translate.h b/target/arm/translate.h > index d42059aa1d..7717ea3f45 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -12,6 +12,12 @@ typedef struct DisasContext { > > /* The address of the current instruction being translated. */ > target_ulong pc_curr; > + /* > + * For TARGET_TB_PCREL, the value relative to pc_curr against which > + * offsets must be computed for cpu_pc. -1 if unknown due to jump. > + */ I'm not really sure what this comment is trying to tell me. Could you expand it a bit ? > + target_ulong pc_save; > + target_ulong pc_cond_save; > target_ulong page_start; > uint32_t insn; > /* Nonzero if this instruction has been conditionally skipped. */ > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 047bf3f4ab..f5e74b6c3b 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -64,17 +64,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) > void arm_cpu_synchronize_from_tb(CPUState *cs, > const TranslationBlock *tb) > { > - ARMCPU *cpu = ARM_CPU(cs); > - CPUARMState *env = &cpu->env; > - > - /* > - * It's OK to look at env for the current mode here, because it's > - * never possible for an AArch64 TB to chain to an AArch32 TB. > - */ > - if (is_a64(env)) { > - env->pc = tb_pc(tb); > - } else { > - env->regs[15] = tb_pc(tb); > + /* The program counter is always up to date with TARGET_TB_PCREL. */ Is it? Is there some documentation in one of the other patchsets about how TARGET_TB_PCREL works in general and what targets need to do to support it? thanks -- PMM