* [Qemu-devel] [PATCH v2 0/4] ARM: exynos4210 PMU modifications
@ 2012-07-12 16:54 Maksim Kozlov
2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 1/4] ARM: exynos4210_pmu: just formatting changes Maksim Kozlov
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Maksim Kozlov @ 2012-07-12 16:54 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, kyungmin.park, e.voevodin
This patchset created mainly to add software reset support, but includes some
other things.
1. fix formatting of the exynos4210_pmu_regs structure
2. fix PRINT_DEBUG macro set to be able to enable extend and non-extend output
independently of each other
3. introduce new function to get register's index
4. add software reset
First three patches are standalone, but the fourth depends on the third.
Changelog:
v1->v2: Deleted the irrelevant comment
Maksim Kozlov (4):
ARM: exynos4210_pmu: just formatting changes
ARM: exynos4210_pmu: changes in PRINT_DEBUG macro set.
ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index
ARM: exynos4210_pmu: Add software reset support
hw/exynos4210_pmu.c | 439 +++++++++++++++++++++++++++++----------------------
1 files changed, 248 insertions(+), 191 deletions(-)
--
1.7.5.4
^ permalink raw reply [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH v2 1/4] ARM: exynos4210_pmu: just formatting changes 2012-07-12 16:54 [Qemu-devel] [PATCH v2 0/4] ARM: exynos4210 PMU modifications Maksim Kozlov @ 2012-07-12 16:54 ` Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 2/4] ARM: exynos4210_pmu: changes in PRINT_DEBUG macro set Maksim Kozlov ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Maksim Kozlov @ 2012-07-12 16:54 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, kyungmin.park, Maksim Kozlov, e.voevodin Mainly to make 'exynos4210_pmu_regs' array more readable. Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com> --- hw/exynos4210_pmu.c | 324 ++++++++++++++++++++++++++------------------------- 1 files changed, 164 insertions(+), 160 deletions(-) diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c index c12d750..2be7e08 100644 --- a/hw/exynos4210_pmu.c +++ b/hw/exynos4210_pmu.c @@ -226,170 +226,174 @@ typedef struct Exynos4210PmuReg { } Exynos4210PmuReg; static const Exynos4210PmuReg exynos4210_pmu_regs[] = { - {"OM_STAT", OM_STAT, 0x00000000}, - {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000}, - {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001}, - {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000}, - {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000}, - {"SWRESET", SWRESET, 0x00000000}, - {"RST_STAT", RST_STAT, 0x00000000}, - {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000}, - {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000}, - {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000}, - {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000}, - {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000}, - {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000}, - {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000}, - {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000}, - {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000}, - {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001}, - {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000}, - {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000}, - {"INFORM0", INFORM0, 0x00000000}, - {"INFORM1", INFORM1, 0x00000000}, - {"INFORM2", INFORM2, 0x00000000}, - {"INFORM3", INFORM3, 0x00000000}, - {"INFORM4", INFORM4, 0x00000000}, - {"INFORM5", INFORM5, 0x00000000}, - {"INFORM6", INFORM6, 0x00000000}, - {"INFORM7", INFORM7, 0x00000000}, - {"PMU_DEBUG", PMU_DEBUG, 0x00000000}, - {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF}, - {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF}, - {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF}, - {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF}, - {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF}, - {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, - {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, - {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, - {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG, - 0xFFFFFFFF}, - {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG, - 0xFFFFFFFF}, - {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, - 0xFFFFFFFF}, - {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, - {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF}, - {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF}, - {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF}, - {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF}, - {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF}, - {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF}, - {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG, - 0xFFFFFFFF}, - {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF}, - {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF}, - {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF}, - {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF}, - {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF}, - {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF}, - {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, - {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF}, - {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF}, - {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF}, - {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF}, - {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF}, - {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF}, - {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, - {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF}, - {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF}, - {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003}, - {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003}, - {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001}, - {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003}, - {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003}, - {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001}, - {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001}, - {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003}, - {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003}, - {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003}, - {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003}, - {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000}, - {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000}, - {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000}, - {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000}, - {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, - {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, - {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, - {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, - {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, - {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, - {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, - {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001}, - {"XXTI_STATUS", XXTI_STATUS, 0x00000001}, - {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000}, - {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF}, - {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007}, - {"CAM_STATUS", CAM_STATUS, 0x00060007}, - {"CAM_OPTION", CAM_OPTION, 0x00000001}, - {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007}, - {"TV_STATUS", TV_STATUS, 0x00060007}, - {"TV_OPTION", TV_OPTION, 0x00000001}, - {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007}, - {"MFC_STATUS", MFC_STATUS, 0x00060007}, - {"MFC_OPTION", MFC_OPTION, 0x00000001}, - {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007}, - {"G3D_STATUS", G3D_STATUS, 0x00060007}, - {"G3D_OPTION", G3D_OPTION, 0x00000001}, - {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007}, - {"LCD0_STATUS", LCD0_STATUS, 0x00060007}, - {"LCD0_OPTION", LCD0_OPTION, 0x00000001}, - {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007}, - {"LCD1_STATUS", LCD1_STATUS, 0x00060007}, - {"LCD1_OPTION", LCD1_OPTION, 0x00000001}, - {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007}, - {"GPS_STATUS", GPS_STATUS, 0x00060007}, - {"GPS_OPTION", GPS_OPTION, 0x00000001}, - {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007}, - {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007}, - {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001}, + { "OM_STAT", OM_STAT, 0x00000000 }, + { "RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000 }, + { "GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001 }, + { "SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000 }, + { "SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000 }, + { "SWRESET", SWRESET, 0x00000000 }, + { "RST_STAT", RST_STAT, 0x00000000 }, + { "WAKEUP_STAT", WAKEUP_STAT, 0x00000000 }, + { "EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000 }, + { "WAKEUP_MASK", WAKEUP_MASK, 0x00000000 }, + { "HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000 }, + { "USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000 }, + { "USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000 }, + { "DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000 }, + { "MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000 }, + { "MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000 }, + { "ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001 }, + { "PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000 }, + { "SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000 }, + { "INFORM0", INFORM0, 0x00000000 }, + { "INFORM1", INFORM1, 0x00000000 }, + { "INFORM2", INFORM2, 0x00000000 }, + { "INFORM3", INFORM3, 0x00000000 }, + { "INFORM4", INFORM4, 0x00000000 }, + { "INFORM5", INFORM5, 0x00000000 }, + { "INFORM6", INFORM6, 0x00000000 }, + { "INFORM7", INFORM7, 0x00000000 }, + { "PMU_DEBUG", PMU_DEBUG, 0x00000000 }, + { "ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF }, + { "ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF }, + { "ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF }, + { "ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF }, + { "ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF }, + { "APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF }, + { "MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF }, + { "VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF }, + { "EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF }, + { "CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF }, + { "TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF }, + { "TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF }, + { "TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF }, + { "LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF }, + { "OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF }, + { "PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG, + 0xFFFFFFFF }, + { "PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF }, + { "PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF }, + { "XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF }, + { "XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF }, + { "EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF }, + { "GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF }, + { "GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, + 0xFFFFFFFF }, + { "CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF }, + { "TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF }, + { "MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF }, + { "G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF }, + { "LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF }, + { "LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF }, + { "MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF }, + { "GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF }, + { "GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF }, + { "ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003 }, + { "ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003 }, + { "ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001 }, + { "ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003 }, + { "ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003 }, + { "ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001 }, + { "ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001 }, + { "ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003 }, + { "ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003 }, + { "ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003 }, + { "ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003 }, + { "PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000 }, + { "PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000 }, + { "PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000 }, + { "PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000 }, + { "PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000 }, + { "PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000 }, + { "PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000 }, + { "PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 }, + { "XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001 }, + { "XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001 }, + { "XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000 }, + { "XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001 }, + { "XXTI_STATUS", XXTI_STATUS, 0x00000001 }, + { "XXTI_DURATION", XXTI_DURATION, 0xFFF00000 }, + { "EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF }, + { "CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007 }, + { "CAM_STATUS", CAM_STATUS, 0x00060007 }, + { "CAM_OPTION", CAM_OPTION, 0x00000001 }, + { "TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007 }, + { "TV_STATUS", TV_STATUS, 0x00060007 }, + { "TV_OPTION", TV_OPTION, 0x00000001 }, + { "MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007 }, + { "MFC_STATUS", MFC_STATUS, 0x00060007 }, + { "MFC_OPTION", MFC_OPTION, 0x00000001 }, + { "G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007 }, + { "G3D_STATUS", G3D_STATUS, 0x00060007 }, + { "G3D_OPTION", G3D_OPTION, 0x00000001 }, + { "LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007 }, + { "LCD0_STATUS", LCD0_STATUS, 0x00060007 }, + { "LCD0_OPTION", LCD0_OPTION, 0x00000001 }, + { "LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007 }, + { "LCD1_STATUS", LCD1_STATUS, 0x00060007 }, + { "LCD1_OPTION", LCD1_OPTION, 0x00000001 }, + { "GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007 }, + { "GPS_STATUS", GPS_STATUS, 0x00060007 }, + { "GPS_OPTION", GPS_OPTION, 0x00000001 }, + { "GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007 }, + { "GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007 }, + { "GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001 }, }; -#define PMU_NUM_OF_REGISTERS \ +#define PMU_NUM_OF_REGISTERS \ (sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg)) typedef struct Exynos4210PmuState { SysBusDevice busdev; MemoryRegion iomem; - uint32_t reg[PMU_NUM_OF_REGISTERS]; + uint32_t reg[PMU_NUM_OF_REGISTERS]; } Exynos4210PmuState; static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset, @@ -468,7 +472,7 @@ static const VMStateDescription exynos4210_pmu_vmstate = { .name = "exynos4210.pmu", .version_id = 1, .minimum_version_id = 1, - .fields = (VMStateField[]) { + .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS), VMSTATE_END_OF_LIST() } @@ -479,9 +483,9 @@ static void exynos4210_pmu_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = exynos4210_pmu_init; + k->init = exynos4210_pmu_init; dc->reset = exynos4210_pmu_reset; - dc->vmsd = &exynos4210_pmu_vmstate; + dc->vmsd = &exynos4210_pmu_vmstate; } static TypeInfo exynos4210_pmu_info = { -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 2/4] ARM: exynos4210_pmu: changes in PRINT_DEBUG macro set. 2012-07-12 16:54 [Qemu-devel] [PATCH v2 0/4] ARM: exynos4210 PMU modifications Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 1/4] ARM: exynos4210_pmu: just formatting changes Maksim Kozlov @ 2012-07-12 16:54 ` Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 3/4] ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support Maksim Kozlov 3 siblings, 0 replies; 9+ messages in thread From: Maksim Kozlov @ 2012-07-12 16:54 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, kyungmin.park, Maksim Kozlov, e.voevodin It make possible to set DEBUG_PMU and DEBUG_PMU_EXTEND independently of each other Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com> --- hw/exynos4210_pmu.c | 23 +++++++++++++++++------ 1 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c index 2be7e08..26a726f 100644 --- a/hw/exynos4210_pmu.c +++ b/hw/exynos4210_pmu.c @@ -34,26 +34,37 @@ #define DEBUG_PMU_EXTEND 0 #endif -#if DEBUG_PMU -#define PRINT_DEBUG(fmt, args...) \ +#if DEBUG_PMU || DEBUG_PMU_EXTEND + + #define PRINT_DEBUG(fmt, args...) \ do { \ fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ } while (0) #if DEBUG_PMU_EXTEND -#define PRINT_DEBUG_EXTEND(fmt, args...) \ + + #define PRINT_DEBUG_EXTEND(fmt, args...) \ do { \ fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ } while (0) #else -#define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) + #define PRINT_DEBUG_EXTEND(fmt, args...) \ + do {} while (0) #endif /* EXTEND */ #else -#define PRINT_DEBUG(fmt, args...) do {} while (0) -#define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) + #define PRINT_DEBUG(fmt, args...) \ + do {} while (0) + #define PRINT_DEBUG_EXTEND(fmt, args...) \ + do {} while (0) #endif +#define PRINT_ERROR(fmt, args...) \ + do { \ + fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ + } while (0) + + /* * Offsets for PMU registers */ -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index 2012-07-12 16:54 [Qemu-devel] [PATCH v2 0/4] ARM: exynos4210 PMU modifications Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 1/4] ARM: exynos4210_pmu: just formatting changes Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 2/4] ARM: exynos4210_pmu: changes in PRINT_DEBUG macro set Maksim Kozlov @ 2012-07-12 16:54 ` Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support Maksim Kozlov 3 siblings, 0 replies; 9+ messages in thread From: Maksim Kozlov @ 2012-07-12 16:54 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, kyungmin.park, Maksim Kozlov, e.voevodin This patch just introduces exynos4210_pmu_get_register_index function to get index of the register's value in the array on its offset. And functions _read and _write were modified accordingly. Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com> --- hw/exynos4210_pmu.c | 56 ++++++++++++++++++++++++++++++++------------------ 1 files changed, 36 insertions(+), 20 deletions(-) diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c index 26a726f..7f09c79 100644 --- a/hw/exynos4210_pmu.c +++ b/hw/exynos4210_pmu.c @@ -401,48 +401,64 @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = { #define PMU_NUM_OF_REGISTERS \ (sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg)) +#define PMU_UNKNOWN_OFFSET 0xFFFFFFFF + typedef struct Exynos4210PmuState { SysBusDevice busdev; MemoryRegion iomem; uint32_t reg[PMU_NUM_OF_REGISTERS]; } Exynos4210PmuState; -static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset, - unsigned size) +static uint32_t exynos4210_pmu_get_register_index(Exynos4210PmuState *s, + uint32_t offset) { - Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; - unsigned i; const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs; + uint32_t i; for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { if (reg_p->offset == offset) { - PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name, - (uint32_t)offset, s->reg[i]); - return s->reg[i]; + return i; } reg_p++; } - PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset); - return 0; + + return PMU_UNKNOWN_OFFSET; +} + +static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; + uint32_t index = exynos4210_pmu_get_register_index(s, offset); + + if (index == PMU_UNKNOWN_OFFSET) { + PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", + (uint32_t)offset); + return 0; + } + + PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", + exynos4210_pmu_regs[index].name, (uint32_t)offset, s->reg[index]); + + return s->reg[index]; } static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, uint64_t val, unsigned size) { Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; - unsigned i; - const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs; + uint32_t index = exynos4210_pmu_get_register_index(s, offset); - for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { - if (reg_p->offset == offset) { - PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, - (uint32_t)offset, (uint32_t)val); - s->reg[i] = val; - return; - } - reg_p++; + if (index == PMU_UNKNOWN_OFFSET) { + PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", + (uint32_t)offset); + return; } - PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset); + + PRINT_DEBUG_EXTEND("%s [0x%04x] <- 0x%04x\n", + exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); + + s->reg[index] = val; } static const MemoryRegionOps exynos4210_pmu_ops = { -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support 2012-07-12 16:54 [Qemu-devel] [PATCH v2 0/4] ARM: exynos4210 PMU modifications Maksim Kozlov ` (2 preceding siblings ...) 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 3/4] ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index Maksim Kozlov @ 2012-07-12 16:54 ` Maksim Kozlov 2012-07-20 14:32 ` Peter Maydell 3 siblings, 1 reply; 9+ messages in thread From: Maksim Kozlov @ 2012-07-12 16:54 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, kyungmin.park, Maksim Kozlov, e.voevodin Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com> --- hw/exynos4210_pmu.c | 40 +++++++++++++++++++++++++++++++++------- 1 files changed, 33 insertions(+), 7 deletions(-) diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c index 7f09c79..96588d9 100644 --- a/hw/exynos4210_pmu.c +++ b/hw/exynos4210_pmu.c @@ -18,13 +18,8 @@ * with this program; if not, see <http://www.gnu.org/licenses/>. */ -/* - * This model implements PMU registers just as a bulk of memory. Currently, - * the only reason this device exists is that secondary CPU boot loader - * uses PMU INFORM5 register as a holding pen. - */ - #include "sysbus.h" +#include "sysemu.h" #ifndef DEBUG_PMU #define DEBUG_PMU 0 @@ -230,6 +225,8 @@ #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c +#define SWRESET_SYSTEM_MASK 0x00000001 + typedef struct Exynos4210PmuReg { const char *name; /* for debug only */ uint32_t offset; @@ -458,7 +455,17 @@ static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, PRINT_DEBUG_EXTEND("%s [0x%04x] <- 0x%04x\n", exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); - s->reg[index] = val; + switch (offset) { + case SWRESET: + if (val & SWRESET_SYSTEM_MASK) { + s->reg[index] = val; + qemu_system_reset_request(); + } + break; + default: + s->reg[index] = val; + break; + } } static const MemoryRegionOps exynos4210_pmu_ops = { @@ -477,9 +484,28 @@ static void exynos4210_pmu_reset(DeviceState *dev) Exynos4210PmuState *s = container_of(dev, Exynos4210PmuState, busdev.qdev); unsigned i; + uint32_t index = exynos4210_pmu_get_register_index(s, SWRESET); + uint32_t swreset = s->reg[index]; /* Set default values for registers */ for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { + if (swreset) { + switch (exynos4210_pmu_regs[i].offset) { + case INFORM0: + case INFORM1: + case INFORM2: + case INFORM3: + case INFORM4: + case INFORM5: + case INFORM6: + case INFORM7: + case PS_HOLD_CONTROL: + /* keep these registers during SW reset */ + continue; + default: + break; + } + } s->reg[i] = exynos4210_pmu_regs[i].reset_value; } } -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support Maksim Kozlov @ 2012-07-20 14:32 ` Peter Maydell 2012-07-23 6:38 ` Maksim Kozlov 2012-07-23 11:01 ` Maksim Kozlov 0 siblings, 2 replies; 9+ messages in thread From: Peter Maydell @ 2012-07-20 14:32 UTC (permalink / raw) To: Maksim Kozlov; +Cc: kyungmin.park, qemu-devel, e.voevodin On 12 July 2012 17:54, Maksim Kozlov <m.kozlov@samsung.com> wrote: > Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com> > --- > hw/exynos4210_pmu.c | 40 +++++++++++++++++++++++++++++++++------- > 1 files changed, 33 insertions(+), 7 deletions(-) > > diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c > index 7f09c79..96588d9 100644 > --- a/hw/exynos4210_pmu.c > +++ b/hw/exynos4210_pmu.c > @@ -18,13 +18,8 @@ > * with this program; if not, see <http://www.gnu.org/licenses/>. > */ > > -/* > - * This model implements PMU registers just as a bulk of memory. Currently, > - * the only reason this device exists is that secondary CPU boot loader > - * uses PMU INFORM5 register as a holding pen. > - */ > - > #include "sysbus.h" > +#include "sysemu.h" > > #ifndef DEBUG_PMU > #define DEBUG_PMU 0 > @@ -230,6 +225,8 @@ > > #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c > > +#define SWRESET_SYSTEM_MASK 0x00000001 > + > typedef struct Exynos4210PmuReg { > const char *name; /* for debug only */ > uint32_t offset; > @@ -458,7 +455,17 @@ static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, > PRINT_DEBUG_EXTEND("%s [0x%04x] <- 0x%04x\n", > exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); > > - s->reg[index] = val; > + switch (offset) { > + case SWRESET: > + if (val & SWRESET_SYSTEM_MASK) { > + s->reg[index] = val; > + qemu_system_reset_request(); > + } > + break; > + default: > + s->reg[index] = val; > + break; > + } > } > > static const MemoryRegionOps exynos4210_pmu_ops = { > @@ -477,9 +484,28 @@ static void exynos4210_pmu_reset(DeviceState *dev) > Exynos4210PmuState *s = > container_of(dev, Exynos4210PmuState, busdev.qdev); > unsigned i; > + uint32_t index = exynos4210_pmu_get_register_index(s, SWRESET); > + uint32_t swreset = s->reg[index]; > > /* Set default values for registers */ > for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { > + if (swreset) { > + switch (exynos4210_pmu_regs[i].offset) { > + case INFORM0: > + case INFORM1: > + case INFORM2: > + case INFORM3: > + case INFORM4: > + case INFORM5: > + case INFORM6: > + case INFORM7: > + case PS_HOLD_CONTROL: > + /* keep these registers during SW reset */ > + continue; > + default: > + break; > + } > + } > s->reg[i] = exynos4210_pmu_regs[i].reset_value; > } > } This patch seems to be trying to make a distinction that QEMU doesn't support, ie between system wide "software reset" and system wide "hard reset". I'm not convinced about the wisdom of trying to paper over this lack with a single-device workaround. -- PMM ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support 2012-07-20 14:32 ` Peter Maydell @ 2012-07-23 6:38 ` Maksim Kozlov 2012-07-23 11:01 ` Maksim Kozlov 1 sibling, 0 replies; 9+ messages in thread From: Maksim Kozlov @ 2012-07-23 6:38 UTC (permalink / raw) To: Peter Maydell; +Cc: kyungmin.park, qemu-devel, e.voevodin 20.07.2012 18:32, Peter Maydell пишет: > On 12 July 2012 17:54, Maksim Kozlov<m.kozlov@samsung.com> wrote: >> Signed-off-by: Maksim Kozlov<m.kozlov@samsung.com> >> --- >> hw/exynos4210_pmu.c | 40 +++++++++++++++++++++++++++++++++------- >> 1 files changed, 33 insertions(+), 7 deletions(-) >> >> diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c >> index 7f09c79..96588d9 100644 >> --- a/hw/exynos4210_pmu.c >> +++ b/hw/exynos4210_pmu.c >> @@ -18,13 +18,8 @@ >> * with this program; if not, see<http://www.gnu.org/licenses/>. >> */ >> >> -/* >> - * This model implements PMU registers just as a bulk of memory. Currently, >> - * the only reason this device exists is that secondary CPU boot loader >> - * uses PMU INFORM5 register as a holding pen. >> - */ >> - >> #include "sysbus.h" >> +#include "sysemu.h" >> >> #ifndef DEBUG_PMU >> #define DEBUG_PMU 0 >> @@ -230,6 +225,8 @@ >> >> #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c >> >> +#define SWRESET_SYSTEM_MASK 0x00000001 >> + >> typedef struct Exynos4210PmuReg { >> const char *name; /* for debug only */ >> uint32_t offset; >> @@ -458,7 +455,17 @@ static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, >> PRINT_DEBUG_EXTEND("%s [0x%04x]<- 0x%04x\n", >> exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); >> >> - s->reg[index] = val; >> + switch (offset) { >> + case SWRESET: >> + if (val& SWRESET_SYSTEM_MASK) { >> + s->reg[index] = val; >> + qemu_system_reset_request(); >> + } >> + break; >> + default: >> + s->reg[index] = val; >> + break; >> + } >> } >> >> static const MemoryRegionOps exynos4210_pmu_ops = { >> @@ -477,9 +484,28 @@ static void exynos4210_pmu_reset(DeviceState *dev) >> Exynos4210PmuState *s = >> container_of(dev, Exynos4210PmuState, busdev.qdev); >> unsigned i; >> + uint32_t index = exynos4210_pmu_get_register_index(s, SWRESET); >> + uint32_t swreset = s->reg[index]; >> >> /* Set default values for registers */ >> for (i = 0; i< PMU_NUM_OF_REGISTERS; i++) { >> + if (swreset) { >> + switch (exynos4210_pmu_regs[i].offset) { >> + case INFORM0: >> + case INFORM1: >> + case INFORM2: >> + case INFORM3: >> + case INFORM4: >> + case INFORM5: >> + case INFORM6: >> + case INFORM7: >> + case PS_HOLD_CONTROL: >> + /* keep these registers during SW reset */ >> + continue; >> + default: >> + break; >> + } >> + } >> s->reg[i] = exynos4210_pmu_regs[i].reset_value; >> } >> } > > This patch seems to be trying to make a distinction that QEMU doesn't > support, ie between system wide "software reset" and system wide > "hard reset". I'm not convinced about the wisdom of trying to paper > over this lack with a single-device workaround. Ok. Thank for review And I found out that this patch contains a mistake, therefore it should be rejected in any case > > -- PMM > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support 2012-07-20 14:32 ` Peter Maydell 2012-07-23 6:38 ` Maksim Kozlov @ 2012-07-23 11:01 ` Maksim Kozlov 2012-07-23 11:05 ` Peter Maydell 1 sibling, 1 reply; 9+ messages in thread From: Maksim Kozlov @ 2012-07-23 11:01 UTC (permalink / raw) To: Peter Maydell; +Cc: kyungmin.park, qemu-devel, e.voevodin 20.07.2012 18:32, Peter Maydell пишет: > On 12 July 2012 17:54, Maksim Kozlov<m.kozlov@samsung.com> wrote: >> Signed-off-by: Maksim Kozlov<m.kozlov@samsung.com> >> --- >> hw/exynos4210_pmu.c | 40 +++++++++++++++++++++++++++++++++------- >> 1 files changed, 33 insertions(+), 7 deletions(-) >> >> diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c >> index 7f09c79..96588d9 100644 >> --- a/hw/exynos4210_pmu.c >> +++ b/hw/exynos4210_pmu.c >> @@ -18,13 +18,8 @@ >> * with this program; if not, see<http://www.gnu.org/licenses/>. >> */ >> >> -/* >> - * This model implements PMU registers just as a bulk of memory. Currently, >> - * the only reason this device exists is that secondary CPU boot loader >> - * uses PMU INFORM5 register as a holding pen. >> - */ >> - >> #include "sysbus.h" >> +#include "sysemu.h" >> >> #ifndef DEBUG_PMU >> #define DEBUG_PMU 0 >> @@ -230,6 +225,8 @@ >> >> #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c >> >> +#define SWRESET_SYSTEM_MASK 0x00000001 >> + >> typedef struct Exynos4210PmuReg { >> const char *name; /* for debug only */ >> uint32_t offset; >> @@ -458,7 +455,17 @@ static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, >> PRINT_DEBUG_EXTEND("%s [0x%04x]<- 0x%04x\n", >> exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); >> >> - s->reg[index] = val; >> + switch (offset) { >> + case SWRESET: >> + if (val& SWRESET_SYSTEM_MASK) { >> + s->reg[index] = val; >> + qemu_system_reset_request(); >> + } >> + break; >> + default: >> + s->reg[index] = val; >> + break; >> + } >> } >> >> static const MemoryRegionOps exynos4210_pmu_ops = { >> @@ -477,9 +484,28 @@ static void exynos4210_pmu_reset(DeviceState *dev) >> Exynos4210PmuState *s = >> container_of(dev, Exynos4210PmuState, busdev.qdev); >> unsigned i; >> + uint32_t index = exynos4210_pmu_get_register_index(s, SWRESET); >> + uint32_t swreset = s->reg[index]; >> >> /* Set default values for registers */ >> for (i = 0; i< PMU_NUM_OF_REGISTERS; i++) { >> + if (swreset) { >> + switch (exynos4210_pmu_regs[i].offset) { >> + case INFORM0: >> + case INFORM1: >> + case INFORM2: >> + case INFORM3: >> + case INFORM4: >> + case INFORM5: >> + case INFORM6: >> + case INFORM7: >> + case PS_HOLD_CONTROL: >> + /* keep these registers during SW reset */ >> + continue; >> + default: >> + break; >> + } >> + } >> s->reg[i] = exynos4210_pmu_regs[i].reset_value; >> } >> } > This patch seems to be trying to make a distinction that QEMU doesn't > support, ie between system wide "software reset" and system wide > "hard reset". I'm not convinced about the wisdom of trying to paper > over this lack with a single-device workaround. Peter, if we add callback (*swreset)() into DeviceClass, whether it will be an acceptable solution? And devices which have different behavior during swreset can register different function for that. What do you think about this? > > -- PMM > -- Best regards, Maksim Kozlov Leading Engineer Advanced Software Group, Samsung Moscow Research Center e-mail: m.kozlov@samsung.com Tel: 7(495) 797-25-00 ext. 3949 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support 2012-07-23 11:01 ` Maksim Kozlov @ 2012-07-23 11:05 ` Peter Maydell 0 siblings, 0 replies; 9+ messages in thread From: Peter Maydell @ 2012-07-23 11:05 UTC (permalink / raw) To: Maksim Kozlov Cc: Anthony Liguori, Evgeny Voevodin, qemu-devel, kyungmin.park, Paolo Bonzini, Andreas Färber On 23 July 2012 12:01, Maksim Kozlov <m.kozlov@samsung.com> wrote: > 20.07.2012 18:32, Peter Maydell пишет: >> This patch seems to be trying to make a distinction that QEMU doesn't >> support, ie between system wide "software reset" and system wide >> "hard reset". I'm not convinced about the wisdom of trying to paper >> over this lack with a single-device workaround. > > Peter, if we add callback (*swreset)() into DeviceClass, whether it will be > an acceptable solution? And devices which have different behavior during > swreset can register different function for that. What do you think about > this? I think reset is a key part of device lifecycle and adding support for 'warm reset' or whatever needs general discussion so we can get the semantics right... cc'ing a couple of people who might have opinions. -- PMM ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2012-07-23 11:06 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-07-12 16:54 [Qemu-devel] [PATCH v2 0/4] ARM: exynos4210 PMU modifications Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 1/4] ARM: exynos4210_pmu: just formatting changes Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 2/4] ARM: exynos4210_pmu: changes in PRINT_DEBUG macro set Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 3/4] ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index Maksim Kozlov 2012-07-12 16:54 ` [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support Maksim Kozlov 2012-07-20 14:32 ` Peter Maydell 2012-07-23 6:38 ` Maksim Kozlov 2012-07-23 11:01 ` Maksim Kozlov 2012-07-23 11:05 ` Peter Maydell
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