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bh=NmG4z32DKSrMHBIzEuBhLqUfjW/cR/ysKSc5rHDmPNM=; b=KJ4yQ5Mq4hojoU+NIY6RJFf1oPNuILCq5sUaS8GFtmVXP0cSID8896VCSBpMYTqSB3 15mQqHojAGGwR66b2jC5FPg6CCeqvt462SjqY3KBFzInJRmex7sB1WrdGZ8HN945PXmG QHgM33SF3TK41ZuqUeE2EtPKf3FD1pi7gQtL6ECOiHJKZJEQQpl5a0flfnQfkGwN5QVD Ha9cRqBJ1hVaL09dWKcoJyBPBWVLc6sSSNMJXpcrcafJD19Q/T+MYnEybkax8nH98nPN qD2Hyi+yAs/qo3B+/cBya3RO7i8zGd/z0TN2+/K4awYHbxANSvNOyILfVz7y74oQJfFR 1bHw== X-Gm-Message-State: ABy/qLb0YNwY5i9sw6CgJjGRLmX7YS0Y39jmPJ12Pyiin/RksUcau7Xu zQzWJM9s1/ABrP3vXZ7kI/ZVv7sl//gRx8kpbDMHCA== X-Google-Smtp-Source: APBJJlG7dK6iHavjpYiSQ6IgZkb2CuIdtEJ7UDXkGBZaBVG6PLqRDud2Z/0oyXP1w3bJSwGCKc/kpIciFOwLiZop5ug= X-Received: by 2002:aa7:d54e:0:b0:521:d770:4753 with SMTP id u14-20020aa7d54e000000b00521d7704753mr2145797edr.13.1689870506685; Thu, 20 Jul 2023 09:28:26 -0700 (PDT) MIME-Version: 1.0 References: <20230719153018.1456180-2-jean-philippe@linaro.org> <20230719153018.1456180-3-jean-philippe@linaro.org> In-Reply-To: <20230719153018.1456180-3-jean-philippe@linaro.org> From: Peter Maydell Date: Thu, 20 Jul 2023 17:28:15 +0100 Message-ID: Subject: Re: [PATCH 1/5] target/arm/ptw: Load stage-2 tables from realm physical space To: Jean-Philippe Brucker Cc: richard.henderson@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 19 Jul 2023 at 16:56, Jean-Philippe Brucker wrote: > > In realm state, stage-2 translation tables are fetched from the realm > physical address space (R_PGRQD). > > Signed-off-by: Jean-Philippe Brucker > --- > target/arm/ptw.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index d1de934702..6318e13b98 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -164,7 +164,11 @@ static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) > * an NS stage 1+2 lookup while the NS bit is 0.) > */ > if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { > - return ARMMMUIdx_Phys_NS; > + if (arm_security_space_below_el3(env) == ARMSS_Realm) { > + return ARMMMUIdx_Phys_Realm; > + } else { > + return ARMMMUIdx_Phys_NS; > + } > } > if (stage2idx == ARMMMUIdx_Stage2_S) { > s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); This isn't wrong, but arm_is_secure_below_el3() calls arm_security_space_below_el3(), so we kinda duplicate work there. I think we should instead have: if (!arm_el_is_aa64(env, 3)) { return ARMMMUIdx_Phys_NS; } switch (arm_security_space_below_el3(env)) { case ARMSS_NonSecure: return ARMMUIdx_Phys_NS; case ARMSS_Realm: return ARMMMUIdx_Phys_Realm; case ARMSS_Secure: [existing code to look at the SW/NSW bits] return s2walk_secure ? ...; default: g_assert_not_reached(); } The comment above the function also needs tweaking to say "SCR_EL3.NS or SCR_EL3.NSE bits" (we do already do the TLB flush in scr_write). thanks -- PMM