From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49991) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZxJS7-00027D-NX for qemu-devel@nongnu.org; Fri, 13 Nov 2015 13:52:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZxJS6-00080J-Oh for qemu-devel@nongnu.org; Fri, 13 Nov 2015 13:52:03 -0500 Received: from mail-yk0-x22b.google.com ([2607:f8b0:4002:c07::22b]:35574) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZxJS6-00080C-Kf for qemu-devel@nongnu.org; Fri, 13 Nov 2015 13:52:02 -0500 Received: by ykba77 with SMTP id a77so161863576ykb.2 for ; Fri, 13 Nov 2015 10:52:02 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1446747358-18214-1-git-send-email-peter.maydell@linaro.org> <1446747358-18214-10-git-send-email-peter.maydell@linaro.org> <56407AC8.9020100@redhat.com> From: Peter Maydell Date: Fri, 13 Nov 2015 18:51:42 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 09/16] target-arm: Support multiple address spaces in page table walks List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Patch Tracking , QEMU Developers , qemu-arm@nongnu.org, "Edgar E. Iglesias" , =?UTF-8?B?QWxleCBCZW5uw6ll?= , =?UTF-8?Q?Andreas_F=C3=A4rber?= On 9 November 2015 at 10:58, Peter Maydell wrote: > On 9 November 2015 at 10:51, Paolo Bonzini wrote: >> >> >> On 05/11/2015 19:15, Peter Maydell wrote: >>> If we have a secure address space, use it in page table walks: >>> * when doing the physical accesses to read descriptors, >>> make them through the correct address space >>> * when the final result indicates a secure access, pass the >>> correct address space index to tlb_set_page_with_attrs() >>> >>> (The descriptor reads are the only direct physical accesses >>> made in target-arm/ for CPUs which might have TrustZone.) >> >> What is the case where you have no secure address space and you have >> TrustZone? KVM doesn't have TrustZone, so it should never be in a >> secure regime, should it? > > You mean "what is the case where is_secure but cpu->num_ases == 1" ? > That happens if you have a TrustZone CPU but the board has only > connected up one address space, because there is no difference > in the view from Secure and NonSecure. (vexpress is like this > in hardware, and most of our board models for TZ CPUS are like > that now even if the real h/w makes a distinction.) Looking more closely at my own code I was wrong here. The case where you have only one AS is when the CPU is using KVM. In that case in theory we should never end up being asked to pick an AddressSpace for a set of MemTxAttrs that say "secure" [in the new design where we figure out the asidx from the txattrs], but it's a bit tricky to be absolutely certain that never happens... thanks -- PMM