From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 11/20] target/arm: Clear unused predicate bits for LD1RQ
Date: Thu, 23 Aug 2018 16:21:28 +0100 [thread overview]
Message-ID: <CAFEAcA-vJu-i2GWy3_WK2BNZj1LhDugb2MnHNMghzc6+O+XeTw@mail.gmail.com> (raw)
In-Reply-To: <20180809042206.15726-12-richard.henderson@linaro.org>
On 9 August 2018 at 05:21, Richard Henderson
<richard.henderson@linaro.org> wrote:
> The 16-byte load only uses 16 predicate bits. But while
> reusing the other load infrastructure, we find other bits
> that are set and trigger an assert. To avoid this and
> retain the assert, zero-extend the predicate that we pass
> to the LD1 helper.
>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-sve.c | 25 +++++++++++++++++++++++--
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index d27bc8c946..bef6b8242d 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -4765,12 +4765,33 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
> unsigned vsz = vec_full_reg_size(s);
> TCGv_ptr t_pg;
> TCGv_i32 desc;
> + int poff;
>
> /* Load the first quadword using the normal predicated load helpers. */
> desc = tcg_const_i32(simd_desc(16, 16, zt));
> - t_pg = tcg_temp_new_ptr();
>
> - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
> + poff = pred_full_reg_offset(s, pg);
> + if (vsz > 16) {
> + /*
> + * Zero-extend the first 16 bits of the predicate into a temporary.
> + * This avoids triggering an assert making sure we don't have bits
> + * set within a predicate beyond VQ, but we have lowered VQ to 1
> + * for this load operation.
> + */
> + TCGv_i64 tmp = tcg_temp_new_i64();
> +#ifdef HOST_WORDS_BIGENDIAN
> + poff += 6;
> +#endif
> + tcg_gen_ld16u_i64(tmp, cpu_env, poff);
> +
> + poff = offsetof(CPUARMState, vfp.preg_tmp);
> + tcg_gen_st_i64(tmp, cpu_env, poff);
> + tcg_temp_free_i64(tmp);
> + }
> +
> + t_pg = tcg_temp_new_ptr();
> + tcg_gen_addi_ptr(t_pg, cpu_env, poff);
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
The bigendian #ifdef in the middle of the code is a little
ugly, though -- I don't suppose it's possible to avoid it
(or abstract it away) somehow?
thanks
-- PMM
next prev parent reply other threads:[~2018-08-23 15:21 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-09 4:21 [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 01/20] target/arm: Set ISAR bits for -cpu max Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 02/20] target/arm: Set ID_AA64PFR0 bits for SVE " Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 03/20] target/arm: Define ID_AA64ZFR0_EL1 Richard Henderson
2018-08-17 15:50 ` Peter Maydell
2018-08-09 4:21 ` [Qemu-devel] [PATCH 04/20] target/arm: Adjust sve_exception_el Richard Henderson
2018-08-17 15:57 ` Peter Maydell
2018-08-09 4:21 ` [Qemu-devel] [PATCH 05/20] target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only Richard Henderson
2018-08-17 16:02 ` Peter Maydell
2018-08-17 16:47 ` Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 06/20] target/arm: Fix arm_current_el for user-only Richard Henderson
2018-08-17 16:03 ` Peter Maydell
2018-08-17 16:51 ` Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 07/20] target/arm: Fix is_a64 " Richard Henderson
2018-08-17 16:03 ` Peter Maydell
2018-08-17 16:10 ` Laurent Desnogues
2018-08-17 16:23 ` Peter Maydell
2018-08-09 4:21 ` [Qemu-devel] [PATCH 08/20] target/arm: Pass in current_el to fp and sve_exception_el Richard Henderson
2018-08-09 18:01 ` Alex Bennée
2018-08-09 18:50 ` Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 09/20] target/arm: Handle SVE vector length changes in system mode Richard Henderson
2018-08-17 16:22 ` Peter Maydell
2018-08-25 19:41 ` Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 10/20] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE Richard Henderson
2018-08-17 16:35 ` Peter Maydell
2018-08-09 4:21 ` [Qemu-devel] [PATCH 11/20] target/arm: Clear unused predicate bits for LD1RQ Richard Henderson
2018-08-23 15:21 ` Peter Maydell [this message]
2018-08-23 15:37 ` Richard Henderson
2018-08-09 4:21 ` [Qemu-devel] [PATCH 12/20] target/arm: Rewrite helper_sve_ld1*_r using pages Richard Henderson
2018-08-10 9:13 ` Alex Bennée
2018-08-10 19:15 ` Richard Henderson
2018-08-23 16:01 ` Peter Maydell
2018-08-09 4:21 ` [Qemu-devel] [PATCH 13/20] target/arm: Rewrite helper_sve_ld[234]*_r Richard Henderson
2018-08-23 16:04 ` Peter Maydell
2018-08-09 4:22 ` [Qemu-devel] [PATCH 14/20] target/arm: Rewrite helper_sve_st[1234]*_r Richard Henderson
2018-08-23 16:06 ` Peter Maydell
2018-08-09 4:22 ` [Qemu-devel] [PATCH 15/20] target/arm: Split contiguous loads for endianness Richard Henderson
2018-08-11 5:40 ` Philippe Mathieu-Daudé
2018-08-09 4:22 ` [Qemu-devel] [PATCH 16/20] target/arm: Split contiguous stores " Richard Henderson
2018-08-11 5:41 ` Philippe Mathieu-Daudé
2018-08-09 4:22 ` [Qemu-devel] [PATCH 17/20] target/arm: Rewrite vector gather loads Richard Henderson
2018-08-23 16:08 ` Peter Maydell
2018-08-09 4:22 ` [Qemu-devel] [PATCH 18/20] target/arm: Rewrite vector gather stores Richard Henderson
2018-08-23 16:09 ` Peter Maydell
2018-08-09 4:22 ` [Qemu-devel] [PATCH 19/20] target/arm: Rewrite vector gather first-fault loads Richard Henderson
2018-08-23 16:10 ` Peter Maydell
2018-08-09 4:22 ` [Qemu-devel] [PATCH 20/20] target/arm: Pass TCGMemOpIdx to sve memory helpers Richard Henderson
2018-08-23 16:23 ` Peter Maydell
2018-08-09 5:48 ` [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches Laurent Desnogues
2018-08-18 9:15 ` no-reply
2018-08-18 10:01 ` no-reply
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