From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWSI-0006ae-Il for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:54:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGWSC-0001Zc-Ch for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:54:18 -0400 Received: from mail-la0-f47.google.com ([209.85.215.47]:39626) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWSC-0001ZM-56 for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:54:12 -0400 Received: by mail-la0-f47.google.com with SMTP id eo20so3661794lab.6 for ; Mon, 02 Sep 2013 08:54:10 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1378136553.2640.34.camel@localhost.localdomain> References: <1378131189-25538-1-git-send-email-marcel.a@redhat.com> <1378131189-25538-4-git-send-email-marcel.a@redhat.com> <1378136553.2640.34.camel@localhost.localdomain> From: Peter Maydell Date: Mon, 2 Sep 2013 16:53:50 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: Paolo Bonzini , Anthony Liguori , QEMU Developers , =?UTF-8?Q?Andreas_F=C3=A4rber?= , "Michael S. Tsirkin" On 2 September 2013 16:42, Marcel Apfelbaum wrote: > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote: >> This is happening at the wrong layer -- you want this memory >> region to be created and managed in the PCI core code so that >> we get correct PCI-spec behaviour for all our PCI controllers, >> not just the two x86 ones you've changed here.pci_address_space > I saw that the memory regions are part of the Host state and > duplicated for each host type(like pci_address_space). > Question, why are not pci_address_space and pci_hole present > in a core layer? > > I followed the existing code; from what you are saying > I understand that also the existing memory regions > like the one mentioned above should be moved in > the core layer, right? Ideally, yes, I think so. However that's not particularly a requirement for the changes you're trying to make here: at the moment what happens is that the pci controller creates the PCI memory and io memory regions (or cheats by reusing the system memory space[*]), passes them to the PCI core code (via pci_bus_new) and then they're the PCI code's responsibility to manage. So in the PCI code you can ignore where they came from when you're deciding how to manage these containers (and in this case what you do is just create your default region and map it in to the container at a suitable priority). [*] I'm pretty sure this is a bug in all platforms that do it. -- PMM