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X-Received-From: 2607:f8b0:4864:20::342 Subject: Re: [Qemu-devel] [PATCH v2 00/21] aspeed: machine extensions and fixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm , QEMU Developers , Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 18 Jun 2019 at 17:53, C=C3=A9dric Le Goater wrote: > > Hello, > > This series improves the current models of the Aspeed machines in QEMU > and adds new ones. It also prepares ground for the future Aspeed SoC. > You will find patches for : > > - per SoC mappings of the memory space and the interrupt number space > - support for multiple CPUs (improved) > - support for multiple NICs > - a RTC model from Joel > - a basic XDMA model from Eddie > - support for multiple CPUs and NICs > - fixes for the irq and timer models from Joel, Andrew and Christian > - DMA support for the SMC controller, which was reworked to use a RAM > container region as suggested by Peter in September 2018 > - new swift-bmc machine from Adriana (P9' processor) Hi; I've left review comments on some of the patches. I'm going to take patches 1-9, 11, 12, 13, 14, 19, 20, 21 into target-arm.next (since we're nearly at softfreeze); the others I either had comments on or they were dependent on earlier patches in the series. thanks -- PMM