* [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-07-12 5:37 ` Boddu, Sai Pavan
2023-07-10 14:02 ` [PATCH v1 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Francisco Iglesias
` (7 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting
CFI data packets between the Xilinx Configuration Frame Unit models
(CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG)
and the Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
MAINTAINERS | 6 ++++
hw/misc/meson.build | 1 +
hw/misc/xlnx-cfi-if.c | 34 ++++++++++++++++++++
include/hw/misc/xlnx-cfi-if.h | 59 +++++++++++++++++++++++++++++++++++
4 files changed, 100 insertions(+)
create mode 100644 hw/misc/xlnx-cfi-if.c
create mode 100644 include/hw/misc/xlnx-cfi-if.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1817cfc62f..3ba115bb9b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1036,6 +1036,12 @@ S: Maintained
F: hw/ssi/xlnx-versal-ospi.c
F: include/hw/ssi/xlnx-versal-ospi.h
+Xilinx Versal CFI
+M: Francisco Iglesias <francisco.iglesias@amd.com>
+S: Maintained
+F: hw/misc/xlnx-cfi-if.c
+F: include/hw/misc/xlnx-cfi-if.h
+
STM32F100
M: Alexandre Iooss <erdnaxe@crans.org>
L: qemu-arm@nongnu.org
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 05877f61cc..9971b1e4db 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -96,6 +96,7 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
+ 'xlnx-cfi-if.c',
))
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
diff --git a/hw/misc/xlnx-cfi-if.c b/hw/misc/xlnx-cfi-if.c
new file mode 100644
index 0000000000..c45f05c4aa
--- /dev/null
+++ b/hw/misc/xlnx-cfi-if.c
@@ -0,0 +1,34 @@
+/*
+ * Xilinx CFI interface
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "hw/misc/xlnx-cfi-if.h"
+
+void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
+{
+ XlnxCfiIfClass *xcic = XLNX_CFI_IF_GET_CLASS(cfi_if);
+
+ if (xcic->cfi_transfer_packet) {
+ xcic->cfi_transfer_packet(cfi_if, pkt);
+ }
+}
+
+static const TypeInfo xlnx_cfi_if_info = {
+ .name = TYPE_XLNX_CFI_IF,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XlnxCfiIfClass),
+};
+
+static void xlnx_cfi_if_register_types(void)
+{
+ type_register_static(&xlnx_cfi_if_info);
+}
+
+type_init(xlnx_cfi_if_register_types)
+
diff --git a/include/hw/misc/xlnx-cfi-if.h b/include/hw/misc/xlnx-cfi-if.h
new file mode 100644
index 0000000000..f9bd12292d
--- /dev/null
+++ b/include/hw/misc/xlnx-cfi-if.h
@@ -0,0 +1,59 @@
+/*
+ * Xilinx CFI interface
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef XLNX_CFI_IF_H
+#define XLNX_CFI_IF_H 1
+
+#include "qemu/help-texts.h"
+#include "hw/hw.h"
+#include "qom/object.h"
+
+#define TYPE_XLNX_CFI_IF "xlnx-cfi-if"
+typedef struct XlnxCfiIfClass XlnxCfiIfClass;
+DECLARE_CLASS_CHECKERS(XlnxCfiIfClass, XLNX_CFI_IF, TYPE_XLNX_CFI_IF)
+
+#define XLNX_CFI_IF(obj) \
+ INTERFACE_CHECK(XlnxCfiIf, (obj), TYPE_XLNX_CFI_IF)
+
+typedef enum {
+ PACKET_TYPE_CFU = 0x52,
+ PACKET_TYPE_CFRAME = 0xA1,
+} xlnx_cfi_packet_type;
+
+typedef enum {
+ CFRAME_FAR = 1,
+ CFRAME_SFR = 2,
+ CFRAME_FDRI = 4,
+ CFRAME_CMD = 6,
+} xlnx_cfi_reg_addr;
+
+typedef struct XlnxCfiPacket {
+ uint8_t reg_addr;
+ uint32_t data[4];
+} XlnxCfiPacket;
+
+typedef struct XlnxCfiIf {
+ Object Parent;
+} XlnxCfiIf;
+
+typedef struct XlnxCfiIfClass {
+ InterfaceClass parent;
+
+ void (*cfi_transfer_packet)(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
+} XlnxCfiIfClass;
+
+/**
+ * Transfer a XlnxCfiPacket.
+ *
+ * @cfi_if: the object implementing this interface
+ * @XlnxCfiPacket: a pointer to the XlnxCfiPacket to transfer
+ */
+void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
+
+#endif /* XLNX_CFI_IF_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* RE: [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface
2023-07-10 14:02 ` [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface Francisco Iglesias
@ 2023-07-12 5:37 ` Boddu, Sai Pavan
0 siblings, 0 replies; 19+ messages in thread
From: Boddu, Sai Pavan @ 2023-07-12 5:37 UTC (permalink / raw)
To: Iglesias, Francisco, qemu-devel@nongnu.org
Cc: frasse.iglesias@gmail.com, alistair@alistair23.me,
edgar.iglesias@gmail.com, peter.maydell@linaro.org,
Konrad, Frederic, Ho, Tong, Garhwal, Vikram
Hi
Looks good.
Reviewed-by: sai.pavan.boddu@amd.com
Regards,
Sai Pavan
>-----Original Message-----
>From: Francisco Iglesias <francisco.iglesias@amd.com>
>Sent: Monday, July 10, 2023 7:33 PM
>To: qemu-devel@nongnu.org
>Cc: frasse.iglesias@gmail.com; alistair@alistair23.me;
>edgar.iglesias@gmail.com; peter.maydell@linaro.org; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>; Ho, Tong <tong.ho@amd.com>; Garhwal,
>Vikram <vikram.garhwal@amd.com>
>Subject: [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface
>
>Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting CFI
>data packets between the Xilinx Configuration Frame Unit models (CFU_APB,
>CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG) and the
>Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when
>emulating bitstream programming and readback).
>
>Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
>---
> MAINTAINERS | 6 ++++
> hw/misc/meson.build | 1 +
> hw/misc/xlnx-cfi-if.c | 34 ++++++++++++++++++++
> include/hw/misc/xlnx-cfi-if.h | 59 +++++++++++++++++++++++++++++++++++
> 4 files changed, 100 insertions(+)
> create mode 100644 hw/misc/xlnx-cfi-if.c create mode 100644
>include/hw/misc/xlnx-cfi-if.h
>
>diff --git a/MAINTAINERS b/MAINTAINERS
>index 1817cfc62f..3ba115bb9b 100644
>--- a/MAINTAINERS
>+++ b/MAINTAINERS
>@@ -1036,6 +1036,12 @@ S: Maintained
> F: hw/ssi/xlnx-versal-ospi.c
> F: include/hw/ssi/xlnx-versal-ospi.h
>
>+Xilinx Versal CFI
>+M: Francisco Iglesias <francisco.iglesias@amd.com>
>+S: Maintained
>+F: hw/misc/xlnx-cfi-if.c
>+F: include/hw/misc/xlnx-cfi-if.h
>+
> STM32F100
> M: Alexandre Iooss <erdnaxe@crans.org>
> L: qemu-arm@nongnu.org
>diff --git a/hw/misc/meson.build b/hw/misc/meson.build index
>05877f61cc..9971b1e4db 100644
>--- a/hw/misc/meson.build
>+++ b/hw/misc/meson.build
>@@ -96,6 +96,7 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true:
>files('xlnx-versal-crl.c'))
> system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
> 'xlnx-versal-xramc.c',
> 'xlnx-versal-pmc-iou-slcr.c',
>+ 'xlnx-cfi-if.c',
> ))
> system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true:
>files('stm32f2xx_syscfg.c'))
> system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true:
>files('stm32f4xx_syscfg.c')) diff --git a/hw/misc/xlnx-cfi-if.c b/hw/misc/xlnx-cfi-
>if.c new file mode 100644 index 0000000000..c45f05c4aa
>--- /dev/null
>+++ b/hw/misc/xlnx-cfi-if.c
>@@ -0,0 +1,34 @@
>+/*
>+ * Xilinx CFI interface
>+ *
>+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
>+ *
>+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
>+ *
>+ * SPDX-License-Identifier: GPL-2.0-or-later */ #include
>+"qemu/osdep.h"
>+#include "hw/misc/xlnx-cfi-if.h"
>+
>+void xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt) {
>+ XlnxCfiIfClass *xcic = XLNX_CFI_IF_GET_CLASS(cfi_if);
>+
>+ if (xcic->cfi_transfer_packet) {
>+ xcic->cfi_transfer_packet(cfi_if, pkt);
>+ }
>+}
>+
>+static const TypeInfo xlnx_cfi_if_info = {
>+ .name = TYPE_XLNX_CFI_IF,
>+ .parent = TYPE_INTERFACE,
>+ .class_size = sizeof(XlnxCfiIfClass), };
>+
>+static void xlnx_cfi_if_register_types(void) {
>+ type_register_static(&xlnx_cfi_if_info);
>+}
>+
>+type_init(xlnx_cfi_if_register_types)
>+
>diff --git a/include/hw/misc/xlnx-cfi-if.h b/include/hw/misc/xlnx-cfi-if.h new file
>mode 100644 index 0000000000..f9bd12292d
>--- /dev/null
>+++ b/include/hw/misc/xlnx-cfi-if.h
>@@ -0,0 +1,59 @@
>+/*
>+ * Xilinx CFI interface
>+ *
>+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
>+ *
>+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
>+ *
>+ * SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef XLNX_CFI_IF_H
>+#define XLNX_CFI_IF_H 1
>+
>+#include "qemu/help-texts.h"
>+#include "hw/hw.h"
>+#include "qom/object.h"
>+
>+#define TYPE_XLNX_CFI_IF "xlnx-cfi-if"
>+typedef struct XlnxCfiIfClass XlnxCfiIfClass;
>+DECLARE_CLASS_CHECKERS(XlnxCfiIfClass, XLNX_CFI_IF, TYPE_XLNX_CFI_IF)
>+
>+#define XLNX_CFI_IF(obj) \
>+ INTERFACE_CHECK(XlnxCfiIf, (obj), TYPE_XLNX_CFI_IF)
>+
>+typedef enum {
>+ PACKET_TYPE_CFU = 0x52,
>+ PACKET_TYPE_CFRAME = 0xA1,
>+} xlnx_cfi_packet_type;
>+
>+typedef enum {
>+ CFRAME_FAR = 1,
>+ CFRAME_SFR = 2,
>+ CFRAME_FDRI = 4,
>+ CFRAME_CMD = 6,
>+} xlnx_cfi_reg_addr;
>+
>+typedef struct XlnxCfiPacket {
>+ uint8_t reg_addr;
>+ uint32_t data[4];
>+} XlnxCfiPacket;
>+
>+typedef struct XlnxCfiIf {
>+ Object Parent;
>+} XlnxCfiIf;
>+
>+typedef struct XlnxCfiIfClass {
>+ InterfaceClass parent;
>+
>+ void (*cfi_transfer_packet)(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
>+} XlnxCfiIfClass;
>+
>+/**
>+ * Transfer a XlnxCfiPacket.
>+ *
>+ * @cfi_if: the object implementing this interface
>+ * @XlnxCfiPacket: a pointer to the XlnxCfiPacket to transfer */ void
>+xlnx_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt);
>+
>+#endif /* XLNX_CFI_IF_H */
>--
>2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
2023-07-10 14:02 ` [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 13:32 ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Francisco Iglesias
` (6 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cfu.c | 373 ++++++++++++++++++++++++++++++
include/hw/misc/xlnx-versal-cfu.h | 212 +++++++++++++++++
4 files changed, 588 insertions(+)
create mode 100644 hw/misc/xlnx-versal-cfu.c
create mode 100644 include/hw/misc/xlnx-versal-cfu.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ba115bb9b..2bc7ab42ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1041,6 +1041,8 @@ M: Francisco Iglesias <francisco.iglesias@amd.com>
S: Maintained
F: hw/misc/xlnx-cfi-if.c
F: include/hw/misc/xlnx-cfi-if.h
+F: hw/misc/xlnx-versal-cfu.c
+F: include/hw/misc/xlnx-versal-cfu.h
STM32F100
M: Alexandre Iooss <erdnaxe@crans.org>
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 9971b1e4db..c88051aa51 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -96,6 +96,7 @@ specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
+ 'xlnx-versal-cfu.c',
'xlnx-cfi-if.c',
))
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c
new file mode 100644
index 0000000000..cbd17d2351
--- /dev/null
+++ b/hw/misc/xlnx-versal-cfu.c
@@ -0,0 +1,373 @@
+/*
+ * QEMU model of the CFU Configuration Unit.
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@gmail.com>,
+ * Sai Pavan Boddu <francisco.iglesias@amd.com>,
+ * Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/irq.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/misc/xlnx-versal-cfu.h"
+
+#ifndef XLNX_VERSAL_CFU_APB_ERR_DEBUG
+#define XLNX_VERSAL_CFU_APB_ERR_DEBUG 0
+#endif
+
+#define KEYHOLE_STREAM_4K 0x1000
+#define KEYHOLE_STREAM_256K 0x40000
+#define CFRAME_BROADCAST_ROW 0x1F
+
+static void cfu_imr_update_irq(XlnxVersalCFUAPB *s)
+{
+ bool pending = s->regs[R_CFU_ISR] & ~s->regs[R_CFU_IMR];
+ qemu_set_irq(s->irq_cfu_imr, pending);
+}
+
+static void cfu_isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
+ cfu_imr_update_irq(s);
+}
+
+static uint64_t cfu_ier_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_CFU_IMR] &= ~val;
+ cfu_imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t cfu_idr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_CFU_IMR] |= val;
+ cfu_imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t cfu_itr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_CFU_ISR] |= val;
+ cfu_imr_update_irq(s);
+ return 0;
+}
+
+static void cfu_fgcr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);
+ uint32_t val = (uint32_t)val64;
+
+ /* Do a scan. It always looks good. */
+ if (FIELD_EX32(val, CFU_FGCR, SC_HBC_TRIGGER)) {
+ ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_PASS, 1);
+ ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_DONE, 1);
+ }
+}
+
+static const RegisterAccessInfo cfu_apb_regs_info[] = {
+ { .name = "CFU_ISR", .addr = A_CFU_ISR,
+ .rsvd = 0xfffffc00,
+ .w1c = 0x3ff,
+ .post_write = cfu_isr_postw,
+ },{ .name = "CFU_IMR", .addr = A_CFU_IMR,
+ .reset = 0x3ff,
+ .rsvd = 0xfffffc00,
+ .ro = 0x3ff,
+ },{ .name = "CFU_IER", .addr = A_CFU_IER,
+ .rsvd = 0xfffffc00,
+ .pre_write = cfu_ier_prew,
+ },{ .name = "CFU_IDR", .addr = A_CFU_IDR,
+ .rsvd = 0xfffffc00,
+ .pre_write = cfu_idr_prew,
+ },{ .name = "CFU_ITR", .addr = A_CFU_ITR,
+ .rsvd = 0xfffffc00,
+ .pre_write = cfu_itr_prew,
+ },{ .name = "CFU_PROTECT", .addr = A_CFU_PROTECT,
+ .reset = 0x1,
+ },{ .name = "CFU_FGCR", .addr = A_CFU_FGCR,
+ .rsvd = 0xffff8000,
+ .post_write = cfu_fgcr_postw,
+ },{ .name = "CFU_CTL", .addr = A_CFU_CTL,
+ .rsvd = 0xffff0000,
+ },{ .name = "CFU_CRAM_RW", .addr = A_CFU_CRAM_RW,
+ .reset = 0x401f7d9,
+ .rsvd = 0xf8000000,
+ },{ .name = "CFU_MASK", .addr = A_CFU_MASK,
+ },{ .name = "CFU_CRC_EXPECT", .addr = A_CFU_CRC_EXPECT,
+ },{ .name = "CFU_CFRAME_LEFT_T0", .addr = A_CFU_CFRAME_LEFT_T0,
+ .rsvd = 0xfff00000,
+ },{ .name = "CFU_CFRAME_LEFT_T1", .addr = A_CFU_CFRAME_LEFT_T1,
+ .rsvd = 0xfff00000,
+ },{ .name = "CFU_CFRAME_LEFT_T2", .addr = A_CFU_CFRAME_LEFT_T2,
+ .rsvd = 0xfff00000,
+ },{ .name = "CFU_ROW_RANGE", .addr = A_CFU_ROW_RANGE,
+ .rsvd = 0xffffffc0,
+ .ro = 0x3f,
+ },{ .name = "CFU_STATUS", .addr = A_CFU_STATUS,
+ .rsvd = 0x80000000,
+ .ro = 0x7fffffff,
+ },{ .name = "CFU_INTERNAL_STATUS", .addr = A_CFU_INTERNAL_STATUS,
+ .rsvd = 0xff800000,
+ .ro = 0x7fffff,
+ },{ .name = "CFU_QWORD_CNT", .addr = A_CFU_QWORD_CNT,
+ .ro = 0xffffffff,
+ },{ .name = "CFU_CRC_LIVE", .addr = A_CFU_CRC_LIVE,
+ .ro = 0xffffffff,
+ },{ .name = "CFU_PENDING_READ_CNT", .addr = A_CFU_PENDING_READ_CNT,
+ .rsvd = 0xfe000000,
+ .ro = 0x1ffffff,
+ },{ .name = "CFU_FDRI_CNT", .addr = A_CFU_FDRI_CNT,
+ .ro = 0xffffffff,
+ },{ .name = "CFU_ECO1", .addr = A_CFU_ECO1,
+ },{ .name = "CFU_ECO2", .addr = A_CFU_ECO2,
+ }
+};
+
+static void cfu_apb_reset(DeviceState *dev)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ s->regs[R_CFU_STATUS] |= R_CFU_STATUS_HC_COMPLETE_MASK;
+ cfu_imr_update_irq(s);
+}
+
+static const MemoryRegionOps cfu_apb_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void cfu_transfer_cfi_packet(XlnxVersalCFUAPB *s, uint8_t row_addr,
+ XlnxCfiPacket *pkt)
+{
+ if (row_addr == CFRAME_BROADCAST_ROW) {
+ for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
+ if (s->cfg.cframe[i]) {
+ xlnx_cfi_transfer_packet(s->cfg.cframe[i], pkt);
+ }
+ }
+ } else {
+ assert(row_addr < ARRAY_SIZE(s->cfg.cframe));
+
+ if (s->cfg.cframe[row_addr]) {
+ xlnx_cfi_transfer_packet(s->cfg.cframe[row_addr], pkt);
+ }
+ }
+}
+
+static uint64_t cfu_stream_read(void *opaque, hwaddr addr, unsigned size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+}
+
+static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(opaque);
+ unsigned int idx;
+
+ /* 4 32bit words. */
+ idx = (addr >> 2) & 3;
+
+ s->wfifo[idx] = value;
+
+ /* Writing to the top word triggers the transmit onto CFI. */
+ if (idx == 3) {
+ uint8_t packet_type, row_addr, reg_addr;
+ int i;
+
+ packet_type = extract32(s->wfifo[0], 24, 8);
+ row_addr = extract32(s->wfifo[0], 16, 5);
+ reg_addr = extract32(s->wfifo[0], 8, 6);
+
+ /* Compressed bitstreams are not supported yet. */
+ if (ARRAY_FIELD_EX32(s->regs, CFU_CTL, DECOMPRESS) == 0) {
+ if (s->regs[R_CFU_FDRI_CNT]) {
+ XlnxCfiPacket pkt = {
+ .reg_addr = CFRAME_FDRI,
+ .data[0] = s->wfifo[0],
+ .data[1] = s->wfifo[1],
+ .data[2] = s->wfifo[2],
+ .data[3] = s->wfifo[3]
+ };
+
+ cfu_transfer_cfi_packet(s, s->fdri_row_addr, &pkt);
+
+ s->regs[R_CFU_FDRI_CNT]--;
+
+ } else if (packet_type == PACKET_TYPE_CFU &&
+ reg_addr == CFRAME_FDRI) {
+
+ /* Load R_CFU_FDRI_CNT, must be multiple of 25 */
+ s->regs[R_CFU_FDRI_CNT] = s->wfifo[1];
+
+ /* Store target row_addr */
+ s->fdri_row_addr = row_addr;
+
+ if (s->wfifo[1] % 25 != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "CFU FDRI_CNT is not loaded with "
+ "a multiple of 25 value\n");
+ }
+
+ } else if (packet_type == PACKET_TYPE_CFRAME) {
+ XlnxCfiPacket pkt = {
+ .reg_addr = reg_addr,
+ .data[0] = s->wfifo[1],
+ .data[1] = s->wfifo[2],
+ .data[2] = s->wfifo[3],
+ };
+ cfu_transfer_cfi_packet(s, row_addr, &pkt);
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->wfifo); i++) {
+ s->wfifo[i] = 0;
+ }
+ }
+}
+
+static const MemoryRegionOps cfu_stream_ops = {
+ .read = cfu_stream_read,
+ .write = cfu_stream_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+};
+
+static void cfu_apb_init(Object *obj)
+{
+ XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+ unsigned int i;
+ char *name;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_VERSAL_CFU_APB, R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), cfu_apb_regs_info,
+ ARRAY_SIZE(cfu_apb_regs_info),
+ s->regs_info, s->regs,
+ &cfu_apb_ops,
+ XLNX_VERSAL_CFU_APB_ERR_DEBUG,
+ R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+ for (i = 0; i < NUM_STREAM; i++) {
+ name = g_strdup_printf(TYPE_XLNX_VERSAL_CFU_APB "-stream%d", i);
+ memory_region_init_io(&s->iomem_stream[i], obj, &cfu_stream_ops, s,
+ name, i == 0 ? KEYHOLE_STREAM_4K :
+ KEYHOLE_STREAM_256K);
+ sysbus_init_mmio(sbd, &s->iomem_stream[i]);
+ g_free(name);
+ }
+ sysbus_init_irq(sbd, &s->irq_cfu_imr);
+}
+
+static Property cfu_props[] = {
+ DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe1", XlnxVersalCFUAPB, cfg.cframe[1],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe2", XlnxVersalCFUAPB, cfg.cframe[2],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe3", XlnxVersalCFUAPB, cfg.cframe[3],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe4", XlnxVersalCFUAPB, cfg.cframe[4],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe5", XlnxVersalCFUAPB, cfg.cframe[5],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe6", XlnxVersalCFUAPB, cfg.cframe[6],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe7", XlnxVersalCFUAPB, cfg.cframe[7],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe8", XlnxVersalCFUAPB, cfg.cframe[8],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe9", XlnxVersalCFUAPB, cfg.cframe[9],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe10", XlnxVersalCFUAPB, cfg.cframe[10],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe11", XlnxVersalCFUAPB, cfg.cframe[11],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe12", XlnxVersalCFUAPB, cfg.cframe[12],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe13", XlnxVersalCFUAPB, cfg.cframe[13],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe14", XlnxVersalCFUAPB, cfg.cframe[14],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static const VMStateDescription vmstate_cfu_apb = {
+ .name = TYPE_XLNX_VERSAL_CFU_APB,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFUAPB, 4),
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalCFUAPB, R_MAX),
+ VMSTATE_UINT8(fdri_row_addr, XlnxVersalCFUAPB),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void cfu_apb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = cfu_apb_reset;
+ dc->vmsd = &vmstate_cfu_apb;
+ device_class_set_props(dc, cfu_props);
+}
+
+static const TypeInfo cfu_apb_info = {
+ .name = TYPE_XLNX_VERSAL_CFU_APB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalCFUAPB),
+ .class_init = cfu_apb_class_init,
+ .instance_init = cfu_apb_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XLNX_CFI_IF },
+ { }
+ }
+};
+
+static void cfu_apb_register_types(void)
+{
+ type_register_static(&cfu_apb_info);
+}
+
+type_init(cfu_apb_register_types)
diff --git a/include/hw/misc/xlnx-versal-cfu.h b/include/hw/misc/xlnx-versal-cfu.h
new file mode 100644
index 0000000000..4936d6e5f0
--- /dev/null
+++ b/include/hw/misc/xlnx-versal-cfu.h
@@ -0,0 +1,212 @@
+/*
+ * QEMU model of the CFU Configuration Unit.
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * References:
+ * [1] Versal ACAP Technical Reference Manual,
+ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
+ *
+ * [2] Versal ACAP Register Reference,
+ * https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
+ */
+#ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H
+#define HW_MISC_XLNX_VERSAL_CFU_APB_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/misc/xlnx-cfi-if.h"
+
+#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
+
+REG32(CFU_ISR, 0x0)
+ FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
+ FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
+ FIELD(CFU_ISR, SLVERR, 7, 1)
+ FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
+ FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
+ FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
+ FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
+ FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
+ FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
+ FIELD(CFU_ISR, SEU_ENDOFCALIB, 0, 1)
+REG32(CFU_IMR, 0x4)
+ FIELD(CFU_IMR, USR_GTS_EVENT, 9, 1)
+ FIELD(CFU_IMR, USR_GSR_EVENT, 8, 1)
+ FIELD(CFU_IMR, SLVERR, 7, 1)
+ FIELD(CFU_IMR, DECOMP_ERROR, 6, 1)
+ FIELD(CFU_IMR, BAD_CFI_PACKET, 5, 1)
+ FIELD(CFU_IMR, AXI_ALIGN_ERROR, 4, 1)
+ FIELD(CFU_IMR, CFI_ROW_ERROR, 3, 1)
+ FIELD(CFU_IMR, CRC32_ERROR, 2, 1)
+ FIELD(CFU_IMR, CRC8_ERROR, 1, 1)
+ FIELD(CFU_IMR, SEU_ENDOFCALIB, 0, 1)
+REG32(CFU_IER, 0x8)
+ FIELD(CFU_IER, USR_GTS_EVENT, 9, 1)
+ FIELD(CFU_IER, USR_GSR_EVENT, 8, 1)
+ FIELD(CFU_IER, SLVERR, 7, 1)
+ FIELD(CFU_IER, DECOMP_ERROR, 6, 1)
+ FIELD(CFU_IER, BAD_CFI_PACKET, 5, 1)
+ FIELD(CFU_IER, AXI_ALIGN_ERROR, 4, 1)
+ FIELD(CFU_IER, CFI_ROW_ERROR, 3, 1)
+ FIELD(CFU_IER, CRC32_ERROR, 2, 1)
+ FIELD(CFU_IER, CRC8_ERROR, 1, 1)
+ FIELD(CFU_IER, SEU_ENDOFCALIB, 0, 1)
+REG32(CFU_IDR, 0xc)
+ FIELD(CFU_IDR, USR_GTS_EVENT, 9, 1)
+ FIELD(CFU_IDR, USR_GSR_EVENT, 8, 1)
+ FIELD(CFU_IDR, SLVERR, 7, 1)
+ FIELD(CFU_IDR, DECOMP_ERROR, 6, 1)
+ FIELD(CFU_IDR, BAD_CFI_PACKET, 5, 1)
+ FIELD(CFU_IDR, AXI_ALIGN_ERROR, 4, 1)
+ FIELD(CFU_IDR, CFI_ROW_ERROR, 3, 1)
+ FIELD(CFU_IDR, CRC32_ERROR, 2, 1)
+ FIELD(CFU_IDR, CRC8_ERROR, 1, 1)
+ FIELD(CFU_IDR, SEU_ENDOFCALIB, 0, 1)
+REG32(CFU_ITR, 0x10)
+ FIELD(CFU_ITR, USR_GTS_EVENT, 9, 1)
+ FIELD(CFU_ITR, USR_GSR_EVENT, 8, 1)
+ FIELD(CFU_ITR, SLVERR, 7, 1)
+ FIELD(CFU_ITR, DECOMP_ERROR, 6, 1)
+ FIELD(CFU_ITR, BAD_CFI_PACKET, 5, 1)
+ FIELD(CFU_ITR, AXI_ALIGN_ERROR, 4, 1)
+ FIELD(CFU_ITR, CFI_ROW_ERROR, 3, 1)
+ FIELD(CFU_ITR, CRC32_ERROR, 2, 1)
+ FIELD(CFU_ITR, CRC8_ERROR, 1, 1)
+ FIELD(CFU_ITR, SEU_ENDOFCALIB, 0, 1)
+REG32(CFU_PROTECT, 0x14)
+ FIELD(CFU_PROTECT, ACTIVE, 0, 1)
+REG32(CFU_FGCR, 0x18)
+ FIELD(CFU_FGCR, GCLK_CAL, 14, 1)
+ FIELD(CFU_FGCR, SC_HBC_TRIGGER, 13, 1)
+ FIELD(CFU_FGCR, GLOW, 12, 1)
+ FIELD(CFU_FGCR, GPWRDWN, 11, 1)
+ FIELD(CFU_FGCR, GCAP, 10, 1)
+ FIELD(CFU_FGCR, GSCWE, 9, 1)
+ FIELD(CFU_FGCR, GHIGH_B, 8, 1)
+ FIELD(CFU_FGCR, GMC_B, 7, 1)
+ FIELD(CFU_FGCR, GWE, 6, 1)
+ FIELD(CFU_FGCR, GRESTORE, 5, 1)
+ FIELD(CFU_FGCR, GTS_CFG_B, 4, 1)
+ FIELD(CFU_FGCR, GLUTMASK, 3, 1)
+ FIELD(CFU_FGCR, EN_GLOBS_B, 2, 1)
+ FIELD(CFU_FGCR, EOS, 1, 1)
+ FIELD(CFU_FGCR, INIT_COMPLETE, 0, 1)
+REG32(CFU_CTL, 0x1c)
+ FIELD(CFU_CTL, GSR_GSC, 15, 1)
+ FIELD(CFU_CTL, SLVERR_EN, 14, 1)
+ FIELD(CFU_CTL, CRC32_RESET, 13, 1)
+ FIELD(CFU_CTL, AXI_ERROR_EN, 12, 1)
+ FIELD(CFU_CTL, FLUSH_AXI, 11, 1)
+ FIELD(CFU_CTL, SSI_PER_SLR_PR, 10, 1)
+ FIELD(CFU_CTL, GCAP_CLK_EN, 9, 1)
+ FIELD(CFU_CTL, STATUS_SYNC_DISABLE, 8, 1)
+ FIELD(CFU_CTL, IGNORE_CFI_ERROR, 7, 1)
+ FIELD(CFU_CTL, CFRAME_DISABLE, 6, 1)
+ FIELD(CFU_CTL, QWORD_CNT_RESET, 5, 1)
+ FIELD(CFU_CTL, CRC8_DISABLE, 4, 1)
+ FIELD(CFU_CTL, CRC32_CHECK, 3, 1)
+ FIELD(CFU_CTL, DECOMPRESS, 2, 1)
+ FIELD(CFU_CTL, SEU_GO, 1, 1)
+ FIELD(CFU_CTL, CFI_LOCAL_RESET, 0, 1)
+REG32(CFU_CRAM_RW, 0x20)
+ FIELD(CFU_CRAM_RW, RFIFO_AFULL_DEPTH, 18, 9)
+ FIELD(CFU_CRAM_RW, RD_WAVE_CNT_LEFT, 12, 6)
+ FIELD(CFU_CRAM_RW, RD_WAVE_CNT, 6, 6)
+ FIELD(CFU_CRAM_RW, WR_WAVE_CNT, 0, 6)
+REG32(CFU_MASK, 0x28)
+REG32(CFU_CRC_EXPECT, 0x2c)
+REG32(CFU_CFRAME_LEFT_T0, 0x60)
+ FIELD(CFU_CFRAME_LEFT_T0, NUM, 0, 20)
+REG32(CFU_CFRAME_LEFT_T1, 0x64)
+ FIELD(CFU_CFRAME_LEFT_T1, NUM, 0, 20)
+REG32(CFU_CFRAME_LEFT_T2, 0x68)
+ FIELD(CFU_CFRAME_LEFT_T2, NUM, 0, 20)
+REG32(CFU_ROW_RANGE, 0x6c)
+ FIELD(CFU_ROW_RANGE, HALF_FSR, 5, 1)
+ FIELD(CFU_ROW_RANGE, NUM, 0, 5)
+REG32(CFU_STATUS, 0x100)
+ FIELD(CFU_STATUS, SEU_WRITE_ERROR, 30, 1)
+ FIELD(CFU_STATUS, FRCNT_ERROR, 29, 1)
+ FIELD(CFU_STATUS, RSVD_ERROR, 28, 1)
+ FIELD(CFU_STATUS, FDRO_ERROR, 27, 1)
+ FIELD(CFU_STATUS, FDRI_ERROR, 26, 1)
+ FIELD(CFU_STATUS, FDRI_READ_ERROR, 25, 1)
+ FIELD(CFU_STATUS, READ_FDRI_ERROR, 24, 1)
+ FIELD(CFU_STATUS, READ_SFR_ERROR, 23, 1)
+ FIELD(CFU_STATUS, READ_STREAM_ERROR, 22, 1)
+ FIELD(CFU_STATUS, UNKNOWN_STREAM_PKT, 21, 1)
+ FIELD(CFU_STATUS, USR_GTS, 20, 1)
+ FIELD(CFU_STATUS, USR_GSR, 19, 1)
+ FIELD(CFU_STATUS, AXI_BAD_WSTRB, 18, 1)
+ FIELD(CFU_STATUS, AXI_BAD_AR_SIZE, 17, 1)
+ FIELD(CFU_STATUS, AXI_BAD_AW_SIZE, 16, 1)
+ FIELD(CFU_STATUS, AXI_BAD_ARADDR, 15, 1)
+ FIELD(CFU_STATUS, AXI_BAD_AWADDR, 14, 1)
+ FIELD(CFU_STATUS, SCAN_CLEAR_PASS, 13, 1)
+ FIELD(CFU_STATUS, HC_SEC_ERROR, 12, 1)
+ FIELD(CFU_STATUS, GHIGH_B_ISHIGH, 11, 1)
+ FIELD(CFU_STATUS, GHIGH_B_ISLOW, 10, 1)
+ FIELD(CFU_STATUS, GMC_B_ISHIGH, 9, 1)
+ FIELD(CFU_STATUS, GMC_B_ISLOW, 8, 1)
+ FIELD(CFU_STATUS, GPWRDWN_B_ISHIGH, 7, 1)
+ FIELD(CFU_STATUS, CFI_SEU_CRC_ERROR, 6, 1)
+ FIELD(CFU_STATUS, CFI_SEU_ECC_ERROR, 5, 1)
+ FIELD(CFU_STATUS, CFI_SEU_HEARTBEAT, 4, 1)
+ FIELD(CFU_STATUS, SCAN_CLEAR_DONE, 3, 1)
+ FIELD(CFU_STATUS, HC_COMPLETE, 2, 1)
+ FIELD(CFU_STATUS, CFI_CFRAME_BUSY, 1, 1)
+ FIELD(CFU_STATUS, CFU_STREAM_BUSY, 0, 1)
+REG32(CFU_INTERNAL_STATUS, 0x104)
+ FIELD(CFU_INTERNAL_STATUS, SSI_EOS, 22, 1)
+ FIELD(CFU_INTERNAL_STATUS, SSI_GWE, 21, 1)
+ FIELD(CFU_INTERNAL_STATUS, RFIFO_EMPTY, 20, 1)
+ FIELD(CFU_INTERNAL_STATUS, RFIFO_FULL, 19, 1)
+ FIELD(CFU_INTERNAL_STATUS, SEL_SFR, 18, 1)
+ FIELD(CFU_INTERNAL_STATUS, STREAM_CFRAME, 17, 1)
+ FIELD(CFU_INTERNAL_STATUS, FDRI_PHASE, 16, 1)
+ FIELD(CFU_INTERNAL_STATUS, CFI_PIPE_EN, 15, 1)
+ FIELD(CFU_INTERNAL_STATUS, AWFIFO_DCNT, 10, 5)
+ FIELD(CFU_INTERNAL_STATUS, WFIFO_DCNT, 5, 5)
+ FIELD(CFU_INTERNAL_STATUS, REPAIR_BUSY, 4, 1)
+ FIELD(CFU_INTERNAL_STATUS, TRIMU_BUSY, 3, 1)
+ FIELD(CFU_INTERNAL_STATUS, TRIMB_BUSY, 2, 1)
+ FIELD(CFU_INTERNAL_STATUS, HCLEANR_BUSY, 1, 1)
+ FIELD(CFU_INTERNAL_STATUS, HCLEAN_BUSY, 0, 1)
+REG32(CFU_QWORD_CNT, 0x108)
+REG32(CFU_CRC_LIVE, 0x10c)
+REG32(CFU_PENDING_READ_CNT, 0x110)
+ FIELD(CFU_PENDING_READ_CNT, NUM, 0, 25)
+REG32(CFU_FDRI_CNT, 0x114)
+REG32(CFU_ECO1, 0x118)
+REG32(CFU_ECO2, 0x11c)
+
+#define R_MAX (R_CFU_ECO2 + 1)
+
+#define NUM_STREAM 2
+
+struct XlnxVersalCFUAPB {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ MemoryRegion iomem_stream[NUM_STREAM];
+ qemu_irq irq_cfu_imr;
+
+ /* 128-bit wfifo. */
+ uint32_t wfifo[4];
+
+ uint32_t regs[R_MAX];
+ RegisterInfo regs_info[R_MAX];
+
+ uint8_t fdri_row_addr;
+
+ struct {
+ XlnxCfiIf *cframe[15];
+ } cfg;
+};
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB
2023-07-10 14:02 ` [PATCH v1 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Francisco Iglesias
@ 2023-08-03 13:32 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 13:32 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Introduce a model of the software programming interface (CFU_APB) of
> Xilinx Versal's Configuration Frame Unit.
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
2023-07-10 14:02 ` [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface Francisco Iglesias
2023-07-10 14:02 ` [PATCH v1 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 13:48 ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Francisco Iglesias
` (5 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
hw/misc/xlnx-versal-cfu.c | 105 ++++++++++++++++++++++++++++++
include/hw/misc/xlnx-versal-cfu.h | 11 ++++
2 files changed, 116 insertions(+)
diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c
index cbd17d2351..528090ef1b 100644
--- a/hw/misc/xlnx-versal-cfu.c
+++ b/hw/misc/xlnx-versal-cfu.c
@@ -257,6 +257,26 @@ static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
}
}
+static uint64_t cfu_fdro_read(void *opaque, hwaddr addr, unsigned size)
+{
+ XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
+ uint64_t ret = 0;
+
+ if (s->fdro_data->len) {
+ ret = g_array_index(s->fdro_data, uint32_t, 0);
+ g_array_remove_index(s->fdro_data, 0);
+ }
+
+ return ret;
+}
+
+static void cfu_fdro_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported write from addr=%"
+ HWADDR_PRIx "\n", __func__, addr);
+}
+
static const MemoryRegionOps cfu_stream_ops = {
.read = cfu_stream_read,
.write = cfu_stream_write,
@@ -267,6 +287,16 @@ static const MemoryRegionOps cfu_stream_ops = {
},
};
+static const MemoryRegionOps cfu_fdro_ops = {
+ .read = cfu_fdro_read,
+ .write = cfu_fdro_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
static void cfu_apb_init(Object *obj)
{
XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
@@ -298,6 +328,24 @@ static void cfu_apb_init(Object *obj)
sysbus_init_irq(sbd, &s->irq_cfu_imr);
}
+static void cfu_fdro_init(Object *obj)
+{
+ XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->iomem_fdro, obj, &cfu_fdro_ops, s,
+ TYPE_XLNX_VERSAL_CFU_FDRO, KEYHOLE_STREAM_4K);
+ sysbus_init_mmio(sbd, &s->iomem_fdro);
+ s->fdro_data = g_array_new(FALSE, FALSE, sizeof(uint32_t));
+}
+
+static void cfu_fdro_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
+{
+ XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(cfi_if);
+
+ g_array_append_vals(s->fdro_data, &pkt->data[0], 4);
+}
+
static Property cfu_props[] = {
DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
TYPE_XLNX_CFI_IF, XlnxCfiIf *),
@@ -344,6 +392,41 @@ static const VMStateDescription vmstate_cfu_apb = {
}
};
+static int cfdro_reg_pre_save(void *opaque)
+{
+ XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
+
+ if (s->fdro_data->len) {
+ s->ro_data = (uint32_t *) s->fdro_data->data;
+ s->ro_dlen = s->fdro_data->len;
+ }
+
+ return 0;
+}
+
+static int cfdro_reg_post_load(void *opaque, int version_id)
+{
+ XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
+
+ if (s->ro_dlen) {
+ g_array_append_vals(s->fdro_data, s->ro_data, s->ro_dlen);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_cfu_fdro = {
+ .name = TYPE_XLNX_VERSAL_CFU_FDRO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_save = cfdro_reg_pre_save,
+ .post_load = cfdro_reg_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32_ALLOC(ro_data, XlnxVersalCFUFDRO, ro_dlen,
+ 0, vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
static void cfu_apb_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -353,6 +436,15 @@ static void cfu_apb_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, cfu_props);
}
+static void cfu_fdro_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ XlnxCfiIfClass *xcic = XLNX_CFI_IF_CLASS(klass);
+
+ dc->vmsd = &vmstate_cfu_fdro;
+ xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;
+}
+
static const TypeInfo cfu_apb_info = {
.name = TYPE_XLNX_VERSAL_CFU_APB,
.parent = TYPE_SYS_BUS_DEVICE,
@@ -365,9 +457,22 @@ static const TypeInfo cfu_apb_info = {
}
};
+static const TypeInfo cfu_fdro_info = {
+ .name = TYPE_XLNX_VERSAL_CFU_FDRO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalCFUFDRO),
+ .class_init = cfu_fdro_class_init,
+ .instance_init = cfu_fdro_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XLNX_CFI_IF },
+ { }
+ }
+};
+
static void cfu_apb_register_types(void)
{
type_register_static(&cfu_apb_info);
+ type_register_static(&cfu_fdro_info);
}
type_init(cfu_apb_register_types)
diff --git a/include/hw/misc/xlnx-versal-cfu.h b/include/hw/misc/xlnx-versal-cfu.h
index 4936d6e5f0..3603bb2862 100644
--- a/include/hw/misc/xlnx-versal-cfu.h
+++ b/include/hw/misc/xlnx-versal-cfu.h
@@ -24,6 +24,9 @@
#define TYPE_XLNX_VERSAL_CFU_APB "xlnx,versal-cfu-apb"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
+#define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx,versal-cfu-fdro"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
+
REG32(CFU_ISR, 0x0)
FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
@@ -209,4 +212,12 @@ struct XlnxVersalCFUAPB {
} cfg;
};
+struct XlnxVersalCFUFDRO {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem_fdro;
+
+ GArray *fdro_data;
+ uint32_t *ro_data;
+ uint32_t ro_dlen;
+};
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
2023-07-10 14:02 ` [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Francisco Iglesias
@ 2023-08-03 13:48 ` Peter Maydell
2023-08-10 19:15 ` Francisco Iglesias
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 13:48 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
> port (CFU_FDRO).
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> hw/misc/xlnx-versal-cfu.c | 105 ++++++++++++++++++++++++++++++
> include/hw/misc/xlnx-versal-cfu.h | 11 ++++
> 2 files changed, 116 insertions(+)
>
> diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c
> index cbd17d2351..528090ef1b 100644
> --- a/hw/misc/xlnx-versal-cfu.c
> +++ b/hw/misc/xlnx-versal-cfu.c
> @@ -257,6 +257,26 @@ static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
> }
> }
>
> +static uint64_t cfu_fdro_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
> + uint64_t ret = 0;
> +
> + if (s->fdro_data->len) {
> + ret = g_array_index(s->fdro_data, uint32_t, 0);
> + g_array_remove_index(s->fdro_data, 0);
This is pretty expensive because everything in the GArray
after element 0 must be copied downwards. Are you sure you
don't want a different data structure ?
What actually is this, and what are the operations we want
to do on it ?
> + }
> +
> + return ret;
> +}
> +
> +static void cfu_fdro_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported write from addr=%"
> + HWADDR_PRIx "\n", __func__, addr);
> +}
> +
> static const MemoryRegionOps cfu_stream_ops = {
> .read = cfu_stream_read,
> .write = cfu_stream_write,
> @@ -267,6 +287,16 @@ static const MemoryRegionOps cfu_stream_ops = {
> },
> };
>
> +static const MemoryRegionOps cfu_fdro_ops = {
> + .read = cfu_fdro_read,
> + .write = cfu_fdro_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> static void cfu_apb_init(Object *obj)
> {
> XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
> @@ -298,6 +328,24 @@ static void cfu_apb_init(Object *obj)
> sysbus_init_irq(sbd, &s->irq_cfu_imr);
> }
>
> +static void cfu_fdro_init(Object *obj)
> +{
> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +
> + memory_region_init_io(&s->iomem_fdro, obj, &cfu_fdro_ops, s,
> + TYPE_XLNX_VERSAL_CFU_FDRO, KEYHOLE_STREAM_4K);
> + sysbus_init_mmio(sbd, &s->iomem_fdro);
> + s->fdro_data = g_array_new(FALSE, FALSE, sizeof(uint32_t));
> +}
> +
> +static void cfu_fdro_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
> +{
> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(cfi_if);
> +
> + g_array_append_vals(s->fdro_data, &pkt->data[0], 4);
> +}
> +
> static Property cfu_props[] = {
> DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
> TYPE_XLNX_CFI_IF, XlnxCfiIf *),
> @@ -344,6 +392,41 @@ static const VMStateDescription vmstate_cfu_apb = {
> }
> };
>
> +static int cfdro_reg_pre_save(void *opaque)
> +{
> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
> +
> + if (s->fdro_data->len) {
> + s->ro_data = (uint32_t *) s->fdro_data->data;
> + s->ro_dlen = s->fdro_data->len;
> + }
I think we need to initialise ro_data and ro_dlen in
the else case here as well. Otherwise they might have old
stale stuff in them that then goes into the migration stream.
> +
> + return 0;
> +}
> +
> +static int cfdro_reg_post_load(void *opaque, int version_id)
> +{
> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
> +
> + if (s->ro_dlen) {
> + g_array_append_vals(s->fdro_data, s->ro_data, s->ro_dlen);
> + }
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_cfu_fdro = {
> + .name = TYPE_XLNX_VERSAL_CFU_FDRO,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .pre_save = cfdro_reg_pre_save,
> + .post_load = cfdro_reg_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_VARRAY_UINT32_ALLOC(ro_data, XlnxVersalCFUFDRO, ro_dlen,
> + 0, vmstate_info_uint32, uint32_t),
This kind of _ALLOC vmstate will cause the migration core
code to g_malloc() you a buffer for the data. We don't
free that anywhere (and if we have a subsequent vmsave
then we will overwrite the ro-data pointer, and leak the
memory).
It might be better to avoid the GArray and just directly
work with a g_malloc()'d buffer of our own, to fit better
with how the _ALLOC vmstate wants to work.
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> static void cfu_apb_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -353,6 +436,15 @@ static void cfu_apb_class_init(ObjectClass *klass, void *data)
> device_class_set_props(dc, cfu_props);
> }
>
> +static void cfu_fdro_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + XlnxCfiIfClass *xcic = XLNX_CFI_IF_CLASS(klass);
> +
> + dc->vmsd = &vmstate_cfu_fdro;
> + xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;
> +}
Missing reset method ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
2023-08-03 13:48 ` Peter Maydell
@ 2023-08-10 19:15 ` Francisco Iglesias
0 siblings, 0 replies; 19+ messages in thread
From: Francisco Iglesias @ 2023-08-10 19:15 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Hi Peter,
On 2023-08-03 15:48, Peter Maydell wrote:
> On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
> <francisco.iglesias@amd.com> wrote:
>>
>> Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
>> port (CFU_FDRO).
>>
>> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
>> ---
>> hw/misc/xlnx-versal-cfu.c | 105 ++++++++++++++++++++++++++++++
>> include/hw/misc/xlnx-versal-cfu.h | 11 ++++
>> 2 files changed, 116 insertions(+)
>>
>> diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c
>> index cbd17d2351..528090ef1b 100644
>> --- a/hw/misc/xlnx-versal-cfu.c
>> +++ b/hw/misc/xlnx-versal-cfu.c
>> @@ -257,6 +257,26 @@ static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
>> }
>> }
>>
>> +static uint64_t cfu_fdro_read(void *opaque, hwaddr addr, unsigned size)
>> +{
>> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
>> + uint64_t ret = 0;
>> +
>> + if (s->fdro_data->len) {
>> + ret = g_array_index(s->fdro_data, uint32_t, 0);
>> + g_array_remove_index(s->fdro_data, 0);
>
> This is pretty expensive because everything in the GArray
> after element 0 must be copied downwards. Are you sure you
> don't want a different data structure ?
>
> What actually is this, and what are the operations we want
> to do on it ?
Thank you very much for reviewing! Regarding above, it is a fifo so
changed to use a Fifo32 in v2 and I also tried to update according to
all other comments!
Best regards,
Francisco Iglesias
>
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void cfu_fdro_write(void *opaque, hwaddr addr, uint64_t value,
>> + unsigned size)
>> +{
>> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported write from addr=%"
>> + HWADDR_PRIx "\n", __func__, addr);
>> +}
>> +
>> static const MemoryRegionOps cfu_stream_ops = {
>> .read = cfu_stream_read,
>> .write = cfu_stream_write,
>> @@ -267,6 +287,16 @@ static const MemoryRegionOps cfu_stream_ops = {
>> },
>> };
>>
>> +static const MemoryRegionOps cfu_fdro_ops = {
>> + .read = cfu_fdro_read,
>> + .write = cfu_fdro_write,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4,
>> + },
>> +};
>> +
>> static void cfu_apb_init(Object *obj)
>> {
>> XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(obj);
>> @@ -298,6 +328,24 @@ static void cfu_apb_init(Object *obj)
>> sysbus_init_irq(sbd, &s->irq_cfu_imr);
>> }
>>
>> +static void cfu_fdro_init(Object *obj)
>> +{
>> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>> +
>> + memory_region_init_io(&s->iomem_fdro, obj, &cfu_fdro_ops, s,
>> + TYPE_XLNX_VERSAL_CFU_FDRO, KEYHOLE_STREAM_4K);
>> + sysbus_init_mmio(sbd, &s->iomem_fdro);
>> + s->fdro_data = g_array_new(FALSE, FALSE, sizeof(uint32_t));
>> +}
>> +
>> +static void cfu_fdro_cfi_transfer_packet(XlnxCfiIf *cfi_if, XlnxCfiPacket *pkt)
>> +{
>> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(cfi_if);
>> +
>> + g_array_append_vals(s->fdro_data, &pkt->data[0], 4);
>> +}
>> +
>> static Property cfu_props[] = {
>> DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB, cfg.cframe[0],
>> TYPE_XLNX_CFI_IF, XlnxCfiIf *),
>> @@ -344,6 +392,41 @@ static const VMStateDescription vmstate_cfu_apb = {
>> }
>> };
>>
>> +static int cfdro_reg_pre_save(void *opaque)
>> +{
>> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
>> +
>> + if (s->fdro_data->len) {
>> + s->ro_data = (uint32_t *) s->fdro_data->data;
>> + s->ro_dlen = s->fdro_data->len;
>> + }
>
> I think we need to initialise ro_data and ro_dlen in
> the else case here as well. Otherwise they might have old
> stale stuff in them that then goes into the migration stream.
>
>> +
>> + return 0;
>> +}
>> +
>> +static int cfdro_reg_post_load(void *opaque, int version_id)
>> +{
>> + XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
>> +
>> + if (s->ro_dlen) {
>> + g_array_append_vals(s->fdro_data, s->ro_data, s->ro_dlen);
>> + }
>> + return 0;
>> +}
>> +
>> +static const VMStateDescription vmstate_cfu_fdro = {
>> + .name = TYPE_XLNX_VERSAL_CFU_FDRO,
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .pre_save = cfdro_reg_pre_save,
>> + .post_load = cfdro_reg_post_load,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_VARRAY_UINT32_ALLOC(ro_data, XlnxVersalCFUFDRO, ro_dlen,
>> + 0, vmstate_info_uint32, uint32_t),
>
> This kind of _ALLOC vmstate will cause the migration core
> code to g_malloc() you a buffer for the data. We don't
> free that anywhere (and if we have a subsequent vmsave
> then we will overwrite the ro-data pointer, and leak the
> memory).
>
> It might be better to avoid the GArray and just directly
> work with a g_malloc()'d buffer of our own, to fit better
> with how the _ALLOC vmstate wants to work.
>
>> + VMSTATE_END_OF_LIST(),
>> + }
>> +};
>> +
>> static void cfu_apb_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> @@ -353,6 +436,15 @@ static void cfu_apb_class_init(ObjectClass *klass, void *data)
>> device_class_set_props(dc, cfu_props);
>> }
>>
>> +static void cfu_fdro_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + XlnxCfiIfClass *xcic = XLNX_CFI_IF_CLASS(klass);
>> +
>> + dc->vmsd = &vmstate_cfu_fdro;
>> + xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;
>> +}
>
> Missing reset method ?
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
` (2 preceding siblings ...)
2023-07-10 14:02 ` [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 13:49 ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Francisco Iglesias
` (4 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
hw/misc/xlnx-versal-cfu.c | 88 +++++++++++++++++++++++++++++++
include/hw/misc/xlnx-versal-cfu.h | 15 ++++++
2 files changed, 103 insertions(+)
diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c
index 528090ef1b..60aec02a58 100644
--- a/hw/misc/xlnx-versal-cfu.c
+++ b/hw/misc/xlnx-versal-cfu.c
@@ -257,6 +257,41 @@ static void cfu_stream_write(void *opaque, hwaddr addr, uint64_t value,
}
}
+static uint64_t cfu_sfr_read(void *opaque, hwaddr addr, unsigned size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+}
+
+static void cfu_sfr_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ XlnxVersalCFUSFR *s = XLNX_VERSAL_CFU_SFR(opaque);
+ unsigned int idx;
+
+ /* 4 32bit words. */
+ idx = (addr >> 2) & 3;
+
+ s->wfifo[idx] = value;
+
+ /* Writing to the top word triggers the transmit onto CFI. */
+ if (idx == 3) {
+ uint8_t row_addr = extract32(s->wfifo[0], 23, 5);
+ uint32_t frame_addr = extract32(s->wfifo[0], 0, 23);
+ XlnxCfiPacket pkt = { .reg_addr = CFRAME_SFR,
+ .data[0] = frame_addr };
+
+ if (s->cfg.cfu) {
+ cfu_transfer_cfi_packet(s->cfg.cfu, row_addr, &pkt);
+ }
+
+ for (int i = 0; i < ARRAY_SIZE(s->wfifo); i++) {
+ s->wfifo[i] = 0;
+ }
+ }
+}
+
static uint64_t cfu_fdro_read(void *opaque, hwaddr addr, unsigned size)
{
XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(opaque);
@@ -287,6 +322,16 @@ static const MemoryRegionOps cfu_stream_ops = {
},
};
+static const MemoryRegionOps cfu_sfr_ops = {
+ .read = cfu_sfr_read,
+ .write = cfu_sfr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
static const MemoryRegionOps cfu_fdro_ops = {
.read = cfu_fdro_read,
.write = cfu_fdro_write,
@@ -328,6 +373,16 @@ static void cfu_apb_init(Object *obj)
sysbus_init_irq(sbd, &s->irq_cfu_imr);
}
+static void cfu_sfr_init(Object *obj)
+{
+ XlnxVersalCFUSFR *s = XLNX_VERSAL_CFU_SFR(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->iomem_sfr, obj, &cfu_sfr_ops, s,
+ TYPE_XLNX_VERSAL_CFU_SFR, KEYHOLE_STREAM_4K);
+ sysbus_init_mmio(sbd, &s->iomem_sfr);
+}
+
static void cfu_fdro_init(Object *obj)
{
XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
@@ -380,6 +435,12 @@ static Property cfu_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static Property cfu_sfr_props[] = {
+ DEFINE_PROP_LINK("cfu", XlnxVersalCFUSFR, cfg.cfu,
+ TYPE_XLNX_VERSAL_CFU_APB, XlnxVersalCFUAPB *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static const VMStateDescription vmstate_cfu_apb = {
.name = TYPE_XLNX_VERSAL_CFU_APB,
.version_id = 1,
@@ -427,6 +488,16 @@ static const VMStateDescription vmstate_cfu_fdro = {
}
};
+static const VMStateDescription vmstate_cfu_sfr = {
+ .name = TYPE_XLNX_VERSAL_CFU_SFR,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFUSFR, 4),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
static void cfu_apb_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -445,6 +516,14 @@ static void cfu_fdro_class_init(ObjectClass *klass, void *data)
xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;
}
+static void cfu_sfr_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ device_class_set_props(dc, cfu_sfr_props);
+ dc->vmsd = &vmstate_cfu_sfr;
+}
+
static const TypeInfo cfu_apb_info = {
.name = TYPE_XLNX_VERSAL_CFU_APB,
.parent = TYPE_SYS_BUS_DEVICE,
@@ -469,10 +548,19 @@ static const TypeInfo cfu_fdro_info = {
}
};
+static const TypeInfo cfu_sfr_info = {
+ .name = TYPE_XLNX_VERSAL_CFU_SFR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalCFUSFR),
+ .class_init = cfu_sfr_class_init,
+ .instance_init = cfu_sfr_init,
+};
+
static void cfu_apb_register_types(void)
{
type_register_static(&cfu_apb_info);
type_register_static(&cfu_fdro_info);
+ type_register_static(&cfu_sfr_info);
}
type_init(cfu_apb_register_types)
diff --git a/include/hw/misc/xlnx-versal-cfu.h b/include/hw/misc/xlnx-versal-cfu.h
index 3603bb2862..add155a8c4 100644
--- a/include/hw/misc/xlnx-versal-cfu.h
+++ b/include/hw/misc/xlnx-versal-cfu.h
@@ -27,6 +27,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
#define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx,versal-cfu-fdro"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
+#define TYPE_XLNX_VERSAL_CFU_SFR "xlnx,versal-cfu-sfr"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUSFR, XLNX_VERSAL_CFU_SFR)
+
REG32(CFU_ISR, 0x0)
FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
@@ -220,4 +223,16 @@ struct XlnxVersalCFUFDRO {
uint32_t *ro_data;
uint32_t ro_dlen;
};
+
+struct XlnxVersalCFUSFR {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem_sfr;
+
+ /* 128-bit wfifo. */
+ uint32_t wfifo[4];
+
+ struct {
+ XlnxVersalCFUAPB *cfu;
+ } cfg;
+};
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
2023-07-10 14:02 ` [PATCH v1 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Francisco Iglesias
@ 2023-08-03 13:49 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 13:49 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
> Frame Read port (CFU_SFR).
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> hw/misc/xlnx-versal-cfu.c | 88 +++++++++++++++++++++++++++++++
> include/hw/misc/xlnx-versal-cfu.h | 15 ++++++
> 2 files changed, 103 insertions(+)
> +static void cfu_sfr_init(Object *obj)
> +{
> + XlnxVersalCFUSFR *s = XLNX_VERSAL_CFU_SFR(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +
> + memory_region_init_io(&s->iomem_sfr, obj, &cfu_sfr_ops, s,
> + TYPE_XLNX_VERSAL_CFU_SFR, KEYHOLE_STREAM_4K);
> + sysbus_init_mmio(sbd, &s->iomem_sfr);
> +}
> +
> static void cfu_fdro_init(Object *obj)
> {
> XlnxVersalCFUFDRO *s = XLNX_VERSAL_CFU_FDRO(obj);
> @@ -380,6 +435,12 @@ static Property cfu_props[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static Property cfu_sfr_props[] = {
> + DEFINE_PROP_LINK("cfu", XlnxVersalCFUSFR, cfg.cfu,
> + TYPE_XLNX_VERSAL_CFU_APB, XlnxVersalCFUAPB *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> static const VMStateDescription vmstate_cfu_apb = {
> .name = TYPE_XLNX_VERSAL_CFU_APB,
> .version_id = 1,
> @@ -427,6 +488,16 @@ static const VMStateDescription vmstate_cfu_fdro = {
> }
> };
>
> +static const VMStateDescription vmstate_cfu_sfr = {
> + .name = TYPE_XLNX_VERSAL_CFU_SFR,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFUSFR, 4),
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> static void cfu_apb_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -445,6 +516,14 @@ static void cfu_fdro_class_init(ObjectClass *klass, void *data)
> xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;
> }
>
> +static void cfu_sfr_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + device_class_set_props(dc, cfu_sfr_props);
> + dc->vmsd = &vmstate_cfu_sfr;
Missing reset again ?
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
` (3 preceding siblings ...)
2023-07-10 14:02 ` [PATCH v1 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 14:01 ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Francisco Iglesias
` (3 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c | 714 +++++++++++++++++++++++
include/hw/misc/xlnx-versal-cframe-reg.h | 288 +++++++++
4 files changed, 1005 insertions(+)
create mode 100644 hw/misc/xlnx-versal-cframe-reg.c
create mode 100644 include/hw/misc/xlnx-versal-cframe-reg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2bc7ab42ae..1fdd6927b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1043,6 +1043,8 @@ F: hw/misc/xlnx-cfi-if.c
F: include/hw/misc/xlnx-cfi-if.h
F: hw/misc/xlnx-versal-cfu.c
F: include/hw/misc/xlnx-versal-cfu.h
+F: hw/misc/xlnx-versal-cframe-reg.c
+F: include/hw/misc/xlnx-versal-cframe-reg.h
STM32F100
M: Alexandre Iooss <erdnaxe@crans.org>
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index c88051aa51..f1ef952004 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -98,6 +98,7 @@ system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-pmc-iou-slcr.c',
'xlnx-versal-cfu.c',
'xlnx-cfi-if.c',
+ 'xlnx-versal-cframe-reg.c',
))
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
diff --git a/hw/misc/xlnx-versal-cframe-reg.c b/hw/misc/xlnx-versal-cframe-reg.c
new file mode 100644
index 0000000000..7e3420e14d
--- /dev/null
+++ b/hw/misc/xlnx-versal-cframe-reg.c
@@ -0,0 +1,714 @@
+/*
+ * QEMU model of the Configuration Frame Control module
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/registerfields.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/misc/xlnx-versal-cframe-reg.h"
+
+#ifndef XLNX_VERSAL_CFRAME_REG_ERR_DEBUG
+#define XLNX_VERSAL_CFRAME_REG_ERR_DEBUG 0
+#endif
+
+#define KEYHOLE_STREAM_4K 0x1000
+
+#define MAX_BLOCKTYPE 6
+#define MAX_BLOCKTYPE_FRAMES 0xFFFFF
+
+enum {
+ CFRAME_CMD_WCFG = 1,
+ CFRAME_CMD_ROWON = 2,
+ CFRAME_CMD_ROWOFF = 3,
+ CFRAME_CMD_RCFG = 4,
+ CFRAME_CMD_DLPARK = 5
+};
+
+static void cfrm_imr_update_irq(XlnxVersalCFrameReg *s)
+{
+ bool pending = s->regs[R_CFRM_ISR0] & ~s->regs[R_CFRM_IMR0];
+ qemu_set_irq(s->irq_cfrm_imr, pending);
+}
+
+static void cfrm_isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+ cfrm_imr_update_irq(s);
+}
+
+static uint64_t cfrm_ier_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ s->regs[R_CFRM_IMR0] &= ~s->regs[R_CFRM_IER0];
+ s->regs[R_CFRM_IER0] = 0;
+ cfrm_imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t cfrm_idr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ s->regs[R_CFRM_IMR0] |= s->regs[R_CFRM_IDR0];
+ s->regs[R_CFRM_IDR0] = 0;
+ cfrm_imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t cfrm_itr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ s->regs[R_CFRM_ISR0] |= s->regs[R_CFRM_ITR0];
+ s->regs[R_CFRM_ITR0] = 0;
+ cfrm_imr_update_irq(s);
+ return 0;
+}
+
+static void cframe_incr_far(XlnxVersalCFrameReg *s)
+{
+ uint32_t faddr = ARRAY_FIELD_EX32(s->regs, FAR0, FRAME_ADDR);
+ uint32_t blktype = ARRAY_FIELD_EX32(s->regs, FAR0, BLOCKTYPE);
+
+ assert(blktype <= MAX_BLOCKTYPE);
+
+ faddr++;
+ if (faddr > s->cfg.blktype_num_frames[blktype]) {
+ /* Restart from 0 and increment block type */
+ faddr = 0;
+ blktype++;
+
+ assert(blktype <= MAX_BLOCKTYPE);
+
+ ARRAY_FIELD_DP32(s->regs, FAR0, BLOCKTYPE, blktype);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, FAR0, FRAME_ADDR, faddr);
+}
+
+static XlnxCFrame *cframes_get_frame(XlnxVersalCFrameReg *s, uint32_t addr)
+{
+ for (int i = 0; i < s->cframes->len; i++) {
+ XlnxCFrame *f = &g_array_index(s->cframes, XlnxCFrame, i);
+
+ if (f->addr == addr) {
+ return f;
+ }
+ }
+ return NULL;
+}
+
+static void cfrm_fdri_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ if (s->row_configured && s->rowon && s->wcfg) {
+ XlnxCFrame *new_f = &s->new_f;
+
+ new_f->data[new_f->idx++] = s->regs[R_FDRI0];
+ new_f->data[new_f->idx++] = s->regs[R_FDRI1];
+ new_f->data[new_f->idx++] = s->regs[R_FDRI2];
+ new_f->data[new_f->idx++] = s->regs[R_FDRI3];
+
+ assert(new_f->idx <= FRAME_NUM_WORDS);
+
+ if (new_f->idx == FRAME_NUM_WORDS) {
+ XlnxCFrame *cur_f;
+
+ /* Include block type and frame address */
+ new_f->addr = extract32(s->regs[R_FAR0], 0, 23);
+
+ cur_f = cframes_get_frame(s, new_f->addr);
+
+ if (cur_f) {
+ /* Overwrite current frame */
+ cur_f[0] = new_f[0];
+ } else {
+ g_array_append_val(s->cframes, new_f[0]);
+ }
+
+ cframe_incr_far(s);
+
+ /* Clear out new_f */
+ memset(new_f, 0, sizeof(*new_f));
+ }
+ }
+}
+
+static void cfrm_readout_frames(XlnxVersalCFrameReg *s, uint32_t start_addr,
+ uint32_t end_addr)
+{
+ for (uint32_t addr = start_addr; addr < end_addr; addr++) {
+ XlnxCFrame *f = cframes_get_frame(s, addr);
+
+ for (int i = 0; i < FRAME_NUM_WORDS; i += 4) {
+ XlnxCfiPacket pkt = {};
+
+ /* If frame was found transmit the data */
+ if (f) {
+ pkt.data[0] = f->data[i];
+ pkt.data[1] = f->data[i + 1];
+ pkt.data[2] = f->data[i + 2];
+ pkt.data[3] = f->data[i + 3];
+ }
+
+ if (s->cfg.cfu_fdro) {
+ xlnx_cfi_transfer_packet(s->cfg.cfu_fdro, &pkt);
+ }
+ }
+ }
+}
+
+static void cfrm_frcnt_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ if (s->row_configured && s->rowon && s->rcfg) {
+ uint32_t start_addr = extract32(s->regs[R_FAR0], 0, 23);
+ uint32_t end_addr = start_addr + s->regs[R_FRCNT0] / FRAME_NUM_QWORDS;
+
+ cfrm_readout_frames(s, start_addr, end_addr);
+ }
+}
+
+static void cfrm_cmd_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ if (s->row_configured) {
+ uint8_t cmd = ARRAY_FIELD_EX32(s->regs, CMD0, CMD);
+
+ switch (cmd) {
+ case CFRAME_CMD_WCFG:
+ s->wcfg = true;
+ break;
+ case CFRAME_CMD_ROWON:
+ s->rowon = true;
+ break;
+ case CFRAME_CMD_ROWOFF:
+ s->rowon = false;
+ break;
+ case CFRAME_CMD_RCFG:
+ s->rcfg = true;
+ break;
+ case CFRAME_CMD_DLPARK:
+ s->wcfg = false;
+ s->rcfg = false;
+ break;
+ default:
+ break;
+ };
+ }
+}
+
+static uint64_t cfrm_last_frame_bot_post_read(RegisterInfo *reg,
+ uint64_t val64)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+ uint64_t val = 0;
+
+ switch (reg->access->addr) {
+ case A_LAST_FRAME_BOT0:
+ val = FIELD_DP32(val, LAST_FRAME_BOT0, BLOCKTYPE1_LAST_FRAME_LSB,
+ s->cfg.blktype_num_frames[1]);
+ val = FIELD_DP32(val, LAST_FRAME_BOT0, BLOCKTYPE0_LAST_FRAME,
+ s->cfg.blktype_num_frames[0]);
+ break;
+ case A_LAST_FRAME_BOT1:
+ val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE3_LAST_FRAME_LSB,
+ s->cfg.blktype_num_frames[3]);
+ val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE2_LAST_FRAME,
+ s->cfg.blktype_num_frames[2]);
+ val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE1_LAST_FRAME_MSB,
+ (s->cfg.blktype_num_frames[1] >> 12));
+ break;
+ case A_LAST_FRAME_BOT2:
+ val = FIELD_DP32(val, LAST_FRAME_BOT2, BLOCKTYPE3_LAST_FRAME_MSB,
+ (s->cfg.blktype_num_frames[3] >> 4));
+ break;
+ case A_LAST_FRAME_BOT3:
+ default:
+ break;
+ }
+
+ return val;
+}
+
+static uint64_t cfrm_last_frame_top_post_read(RegisterInfo *reg,
+ uint64_t val64)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+ uint64_t val = 0;
+
+ switch (reg->access->addr) {
+ case A_LAST_FRAME_TOP0:
+ val = FIELD_DP32(val, LAST_FRAME_TOP0, BLOCKTYPE5_LAST_FRAME_LSB,
+ s->cfg.blktype_num_frames[5]);
+ val = FIELD_DP32(val, LAST_FRAME_TOP0, BLOCKTYPE4_LAST_FRAME,
+ s->cfg.blktype_num_frames[4]);
+ break;
+ case A_LAST_FRAME_TOP1:
+ val = FIELD_DP32(val, LAST_FRAME_TOP1, BLOCKTYPE6_LAST_FRAME,
+ s->cfg.blktype_num_frames[6]);
+ val = FIELD_DP32(val, LAST_FRAME_TOP1, BLOCKTYPE5_LAST_FRAME_MSB,
+ (s->cfg.blktype_num_frames[5] >> 12));
+ break;
+ case A_LAST_FRAME_TOP2:
+ case A_LAST_FRAME_BOT3:
+ default:
+ break;
+ }
+
+ return val;
+}
+
+static void cfrm_far_sfr_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
+
+ if (s->row_configured && s->rowon && s->rcfg) {
+ uint32_t start_addr = extract32(s->regs[R_FAR_SFR0], 0, 23);
+
+ /* Readback 1 frame */
+ cfrm_readout_frames(s, start_addr, start_addr + 1);
+ }
+}
+
+static const RegisterAccessInfo cframe_reg_regs_info[] = {
+ { .name = "CRC0", .addr = A_CRC0,
+ .rsvd = 0x00000000,
+ },{ .name = "CRC1", .addr = A_CRC0,
+ .rsvd = 0xffffffff,
+ },{ .name = "CRC2", .addr = A_CRC0,
+ .rsvd = 0xffffffff,
+ },{ .name = "CRC3", .addr = A_CRC0,
+ .rsvd = 0xffffffff,
+ },{ .name = "FAR0", .addr = A_FAR0,
+ .rsvd = 0xfe000000,
+ },{ .name = "FAR1", .addr = A_FAR1,
+ .rsvd = 0xffffffff,
+ },{ .name = "FAR2", .addr = A_FAR2,
+ .rsvd = 0xffffffff,
+ },{ .name = "FAR3", .addr = A_FAR3,
+ .rsvd = 0xffffffff,
+ },{ .name = "FAR_SFR0", .addr = A_FAR_SFR0,
+ .rsvd = 0xff800000,
+ },{ .name = "FAR_SFR1", .addr = A_FAR_SFR1,
+ .rsvd = 0xffffffff,
+ },{ .name = "FAR_SFR2", .addr = A_FAR_SFR2,
+ .rsvd = 0xffffffff,
+ },{ .name = "FAR_SFR3", .addr = A_FAR_SFR3,
+ .rsvd = 0xffffffff,
+ .post_write = cfrm_far_sfr_post_write,
+ },{ .name = "FDRI0", .addr = A_FDRI0,
+ },{ .name = "FDRI1", .addr = A_FDRI1,
+ },{ .name = "FDRI2", .addr = A_FDRI2,
+ },{ .name = "FDRI3", .addr = A_FDRI3,
+ .post_write = cfrm_fdri_post_write,
+ },{ .name = "FRCNT0", .addr = A_FRCNT0,
+ .rsvd = 0x00000000,
+ },{ .name = "FRCNT1", .addr = A_FRCNT1,
+ .rsvd = 0xffffffff,
+ },{ .name = "FRCNT2", .addr = A_FRCNT2,
+ .rsvd = 0xffffffff,
+ },{ .name = "FRCNT3", .addr = A_FRCNT3,
+ .rsvd = 0xffffffff,
+ .post_write = cfrm_frcnt_post_write
+ },{ .name = "CMD0", .addr = A_CMD0,
+ .rsvd = 0xffffffe0,
+ },{ .name = "CMD1", .addr = A_CMD1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CMD2", .addr = A_CMD2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CMD3", .addr = A_CMD3,
+ .rsvd = 0xffffffff,
+ .post_write = cfrm_cmd_post_write
+ },{ .name = "CR_MASK0", .addr = A_CR_MASK0,
+ .rsvd = 0x00000000,
+ },{ .name = "CR_MASK1", .addr = A_CR_MASK1,
+ .rsvd = 0x00000000,
+ },{ .name = "CR_MASK2", .addr = A_CR_MASK2,
+ .rsvd = 0x00000000,
+ },{ .name = "CR_MASK3", .addr = A_CR_MASK3,
+ .rsvd = 0xffffffff,
+ },{ .name = "CTL0", .addr = A_CTL0,
+ .rsvd = 0xfffffff8,
+ },{ .name = "CTL1", .addr = A_CTL1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CTL2", .addr = A_CTL2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CTL3", .addr = A_CTL3,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_ISR0", .addr = A_CFRM_ISR0,
+ .rsvd = 0xffc04000,
+ .w1c = 0x3bfff,
+ },{ .name = "CFRM_ISR1", .addr = A_CFRM_ISR1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_ISR2", .addr = A_CFRM_ISR2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_ISR3", .addr = A_CFRM_ISR3,
+ .rsvd = 0xffffffff,
+ .post_write = cfrm_isr_postw,
+ },{ .name = "CFRM_IMR0", .addr = A_CFRM_IMR0,
+ .rsvd = 0xffc04000,
+ .ro = 0xfffff,
+ .reset = 0x3bfff,
+ },{ .name = "CFRM_IMR1", .addr = A_CFRM_IMR1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IMR2", .addr = A_CFRM_IMR2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IMR3", .addr = A_CFRM_IMR3,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IER0", .addr = A_CFRM_IER0,
+ .rsvd = 0xffc04000,
+ },{ .name = "CFRM_IER1", .addr = A_CFRM_IER1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IER2", .addr = A_CFRM_IER2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IER3", .addr = A_CFRM_IER3,
+ .rsvd = 0xffffffff,
+ .pre_write = cfrm_ier_prew,
+ },{ .name = "CFRM_IDR0", .addr = A_CFRM_IDR0,
+ .rsvd = 0xffc04000,
+ },{ .name = "CFRM_IDR1", .addr = A_CFRM_IDR1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IDR2", .addr = A_CFRM_IDR2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_IDR3", .addr = A_CFRM_IDR3,
+ .rsvd = 0xffffffff,
+ .pre_write = cfrm_idr_prew,
+ },{ .name = "CFRM_ITR0", .addr = A_CFRM_ITR0,
+ .rsvd = 0xffc04000,
+ },{ .name = "CFRM_ITR1", .addr = A_CFRM_ITR1,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_ITR2", .addr = A_CFRM_ITR2,
+ .rsvd = 0xffffffff,
+ },{ .name = "CFRM_ITR3", .addr = A_CFRM_ITR3,
+ .rsvd = 0xffffffff,
+ .pre_write = cfrm_itr_prew,
+ },{ .name = "SEU_SYNDRM00", .addr = A_SEU_SYNDRM00,
+ },{ .name = "SEU_SYNDRM01", .addr = A_SEU_SYNDRM01,
+ },{ .name = "SEU_SYNDRM02", .addr = A_SEU_SYNDRM02,
+ },{ .name = "SEU_SYNDRM03", .addr = A_SEU_SYNDRM03,
+ },{ .name = "SEU_SYNDRM10", .addr = A_SEU_SYNDRM10,
+ },{ .name = "SEU_SYNDRM11", .addr = A_SEU_SYNDRM11,
+ },{ .name = "SEU_SYNDRM12", .addr = A_SEU_SYNDRM12,
+ },{ .name = "SEU_SYNDRM13", .addr = A_SEU_SYNDRM13,
+ },{ .name = "SEU_SYNDRM20", .addr = A_SEU_SYNDRM20,
+ },{ .name = "SEU_SYNDRM21", .addr = A_SEU_SYNDRM21,
+ },{ .name = "SEU_SYNDRM22", .addr = A_SEU_SYNDRM22,
+ },{ .name = "SEU_SYNDRM23", .addr = A_SEU_SYNDRM23,
+ },{ .name = "SEU_SYNDRM30", .addr = A_SEU_SYNDRM30,
+ },{ .name = "SEU_SYNDRM31", .addr = A_SEU_SYNDRM31,
+ },{ .name = "SEU_SYNDRM32", .addr = A_SEU_SYNDRM32,
+ },{ .name = "SEU_SYNDRM33", .addr = A_SEU_SYNDRM33,
+ },{ .name = "SEU_VIRTUAL_SYNDRM0", .addr = A_SEU_VIRTUAL_SYNDRM0,
+ },{ .name = "SEU_VIRTUAL_SYNDRM1", .addr = A_SEU_VIRTUAL_SYNDRM1,
+ },{ .name = "SEU_VIRTUAL_SYNDRM2", .addr = A_SEU_VIRTUAL_SYNDRM2,
+ },{ .name = "SEU_VIRTUAL_SYNDRM3", .addr = A_SEU_VIRTUAL_SYNDRM3,
+ },{ .name = "SEU_CRC0", .addr = A_SEU_CRC0,
+ },{ .name = "SEU_CRC1", .addr = A_SEU_CRC1,
+ },{ .name = "SEU_CRC2", .addr = A_SEU_CRC2,
+ },{ .name = "SEU_CRC3", .addr = A_SEU_CRC3,
+ },{ .name = "CFRAME_FAR_BOT0", .addr = A_CFRAME_FAR_BOT0,
+ },{ .name = "CFRAME_FAR_BOT1", .addr = A_CFRAME_FAR_BOT1,
+ },{ .name = "CFRAME_FAR_BOT2", .addr = A_CFRAME_FAR_BOT2,
+ },{ .name = "CFRAME_FAR_BOT3", .addr = A_CFRAME_FAR_BOT3,
+ },{ .name = "CFRAME_FAR_TOP0", .addr = A_CFRAME_FAR_TOP0,
+ },{ .name = "CFRAME_FAR_TOP1", .addr = A_CFRAME_FAR_TOP1,
+ },{ .name = "CFRAME_FAR_TOP2", .addr = A_CFRAME_FAR_TOP2,
+ },{ .name = "CFRAME_FAR_TOP3", .addr = A_CFRAME_FAR_TOP3,
+ },{ .name = "LAST_FRAME_BOT0", .addr = A_LAST_FRAME_BOT0,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_bot_post_read,
+ },{ .name = "LAST_FRAME_BOT1", .addr = A_LAST_FRAME_BOT1,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_bot_post_read,
+ },{ .name = "LAST_FRAME_BOT2", .addr = A_LAST_FRAME_BOT2,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_bot_post_read,
+ },{ .name = "LAST_FRAME_BOT3", .addr = A_LAST_FRAME_BOT3,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_bot_post_read,
+ },{ .name = "LAST_FRAME_TOP0", .addr = A_LAST_FRAME_TOP0,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_top_post_read,
+ },{ .name = "LAST_FRAME_TOP1", .addr = A_LAST_FRAME_TOP1,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_top_post_read,
+ },{ .name = "LAST_FRAME_TOP2", .addr = A_LAST_FRAME_TOP2,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_top_post_read,
+ },{ .name = "LAST_FRAME_TOP3", .addr = A_LAST_FRAME_TOP3,
+ .ro = 0xffffffff,
+ .post_read = cfrm_last_frame_top_post_read,
+ }
+};
+
+static void cframe_reg_cfi_transfer_packet(XlnxCfiIf *cfi_if,
+ XlnxCfiPacket *pkt)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(cfi_if);
+ uint64_t we = MAKE_64BIT_MASK(0, 4 * 8);
+
+ if (!s->row_configured) {
+ return;
+ }
+
+ switch (pkt->reg_addr) {
+ case CFRAME_FAR:
+ s->regs[R_FAR0] = pkt->data[0];
+ break;
+ case CFRAME_SFR:
+ s->regs[R_FAR_SFR0] = pkt->data[0];
+ register_write(&s->regs_info[R_FAR_SFR3], 0,
+ we, object_get_typename(OBJECT(s)),
+ XLNX_VERSAL_CFRAME_REG_ERR_DEBUG);
+ break;
+ case CFRAME_FDRI:
+ {
+ s->regs[R_FDRI0] = pkt->data[0];
+ s->regs[R_FDRI1] = pkt->data[1];
+ s->regs[R_FDRI2] = pkt->data[2];
+ register_write(&s->regs_info[R_FDRI3], pkt->data[3],
+ we, object_get_typename(OBJECT(s)),
+ XLNX_VERSAL_CFRAME_REG_ERR_DEBUG);
+ break;
+ }
+ case CFRAME_CMD:
+ ARRAY_FIELD_DP32(s->regs, CMD0, CMD, pkt->data[0]);
+
+ register_write(&s->regs_info[R_CMD3], 0,
+ we, object_get_typename(OBJECT(s)),
+ XLNX_VERSAL_CFRAME_REG_ERR_DEBUG);
+ break;
+ default:
+ break;
+ }
+}
+
+static uint64_t cframe_reg_fdri_read(void *opaque, hwaddr addr, unsigned size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+}
+
+static void cframe_reg_fdri_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(opaque);
+ unsigned int idx;
+
+ /* 4 32bit words. */
+ idx = (addr >> 2) & 3;
+
+ s->wfifo[idx] = value;
+
+ /* Writing to the top word triggers the forwarding to the FDRI. */
+ if (idx == 3) {
+ uint64_t we = MAKE_64BIT_MASK(0, 4 * 8);
+
+ s->regs[R_FDRI0] = s->wfifo[0];
+ s->regs[R_FDRI1] = s->wfifo[1];
+ s->regs[R_FDRI2] = s->wfifo[2];
+ register_write(&s->regs_info[R_FDRI3], s->wfifo[3],
+ we, object_get_typename(OBJECT(s)),
+ XLNX_VERSAL_CFRAME_REG_ERR_DEBUG);
+
+ memset(s->wfifo, 0, 4 * sizeof(uint32_t));
+ }
+}
+
+static void cframe_reg_reset_enter(Object *obj, ResetType type)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void cframe_reg_reset_hold(Object *obj)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj);
+
+ cfrm_imr_update_irq(s);
+}
+
+static const MemoryRegionOps cframe_reg_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static const MemoryRegionOps cframe_reg_fdri_ops = {
+ .read = cframe_reg_fdri_read,
+ .write = cframe_reg_fdri_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void cframe_reg_realize(DeviceState *dev, Error **errp)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(dev);
+
+ for (int i = 0; i < ARRAY_SIZE(s->cfg.blktype_num_frames); i++) {
+ if (s->cfg.blktype_num_frames[i] > MAX_BLOCKTYPE_FRAMES) {
+ error_setg(errp,
+ "blktype-frames%d > 0xFFFFF (max frame per block)",
+ i);
+ return;
+ }
+ if (s->cfg.blktype_num_frames[i]) {
+ s->row_configured = true;
+ }
+ }
+}
+
+static void cframe_reg_init(Object *obj)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_VERSAL_CFRAME_REG,
+ CFRAME_REG_R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), cframe_reg_regs_info,
+ ARRAY_SIZE(cframe_reg_regs_info),
+ s->regs_info, s->regs,
+ &cframe_reg_ops,
+ XLNX_VERSAL_CFRAME_REG_ERR_DEBUG,
+ CFRAME_REG_R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+ memory_region_init_io(&s->iomem_fdri, obj, &cframe_reg_fdri_ops, s,
+ TYPE_XLNX_VERSAL_CFRAME_REG "-fdri",
+ KEYHOLE_STREAM_4K);
+ sysbus_init_mmio(sbd, &s->iomem_fdri);
+ sysbus_init_irq(sbd, &s->irq_cfrm_imr);
+
+ s->cframes = g_array_new(FALSE, FALSE, sizeof(XlnxCFrame));
+}
+
+static int cframes_reg_pre_save(void *opaque)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(opaque);
+
+ if (s->cframes->len) {
+ s->cf_data = (uint32_t *) s->cframes->data;
+ s->cf_dlen = s->cframes->len * g_array_get_element_size(s->cframes) / 4;
+ }
+ return 0;
+}
+
+static int cframes_reg_post_load(void *opaque, int version_id)
+{
+ XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(opaque);
+
+ if (s->cf_dlen) {
+ uint32_t num_frames = s->cf_dlen /
+ (g_array_get_element_size(s->cframes) / 4);
+ g_array_append_vals(s->cframes, s->cf_data, num_frames);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_cframe_reg = {
+ .name = TYPE_XLNX_VERSAL_CFRAME_REG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_save = cframes_reg_pre_save,
+ .post_load = cframes_reg_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFrameReg, 4),
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalCFrameReg, CFRAME_REG_R_MAX),
+ VMSTATE_BOOL(rowon, XlnxVersalCFrameReg),
+ VMSTATE_BOOL(wcfg, XlnxVersalCFrameReg),
+ VMSTATE_BOOL(rcfg, XlnxVersalCFrameReg),
+ VMSTATE_VARRAY_UINT32_ALLOC(cf_data, XlnxVersalCFrameReg, cf_dlen,
+ 0, vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property cframe_regs_props[] = {
+ /* Kept for backwards compatibility */
+ DEFINE_PROP_LINK("cfu", XlnxVersalCFrameReg, cfg.cfu_fdro,
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cfu-fdro", XlnxVersalCFrameReg, cfg.cfu_fdro,
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_UINT32("blktype0-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[0], 0),
+ DEFINE_PROP_UINT32("blktype1-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[1], 0),
+ DEFINE_PROP_UINT32("blktype2-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[2], 0),
+ DEFINE_PROP_UINT32("blktype3-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[3], 0),
+ DEFINE_PROP_UINT32("blktype4-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[4], 0),
+ DEFINE_PROP_UINT32("blktype5-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[5], 0),
+ DEFINE_PROP_UINT32("blktype6-frames", XlnxVersalCFrameReg,
+ cfg.blktype_num_frames[6], 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void cframe_reg_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ XlnxCfiIfClass *xcic = XLNX_CFI_IF_CLASS(klass);
+
+ dc->vmsd = &vmstate_cframe_reg;
+ dc->realize = cframe_reg_realize;
+ rc->phases.enter = cframe_reg_reset_enter;
+ rc->phases.hold = cframe_reg_reset_hold;
+ device_class_set_props(dc, cframe_regs_props);
+ xcic->cfi_transfer_packet = cframe_reg_cfi_transfer_packet;
+}
+
+static const TypeInfo cframe_reg_info = {
+ .name = TYPE_XLNX_VERSAL_CFRAME_REG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalCFrameReg),
+ .class_init = cframe_reg_class_init,
+ .instance_init = cframe_reg_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XLNX_CFI_IF },
+ { }
+ }
+};
+
+static void cframe_reg_register_types(void)
+{
+ type_register_static(&cframe_reg_info);
+}
+
+type_init(cframe_reg_register_types)
diff --git a/include/hw/misc/xlnx-versal-cframe-reg.h b/include/hw/misc/xlnx-versal-cframe-reg.h
new file mode 100644
index 0000000000..07dd9ed3e4
--- /dev/null
+++ b/include/hw/misc/xlnx-versal-cframe-reg.h
@@ -0,0 +1,288 @@
+/*
+ * QEMU model of the Configuration Frame Control module
+ *
+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
+ *
+ * Written by Francisco Iglesias <francisco.iglesias@amd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * References:
+ * [1] Versal ACAP Technical Reference Manual,
+ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
+ *
+ * [2] Versal ACAP Register Reference,
+ * https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
+ */
+#ifndef HW_MISC_XLNX_VERSAL_CFRAME_REG_H
+#define HW_MISC_XLNX_VERSAL_CFRAME_REG_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/misc/xlnx-cfi-if.h"
+
+#define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx,cframe-reg"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameReg, XLNX_VERSAL_CFRAME_REG)
+
+/*
+ * The registers in this module are 128 bits wide but it is ok to write
+ * and read them through 4 sequential 32 bit accesses (address[3:2] = 0,
+ * 1, 2, 3).
+ */
+REG32(CRC0, 0x0)
+ FIELD(CRC, CRC, 0, 32)
+REG32(CRC1, 0x4)
+REG32(CRC2, 0x8)
+REG32(CRC3, 0xc)
+REG32(FAR0, 0x10)
+ FIELD(FAR0, SEGMENT, 23, 2)
+ FIELD(FAR0, BLOCKTYPE, 20, 3)
+ FIELD(FAR0, FRAME_ADDR, 0, 20)
+REG32(FAR1, 0x14)
+REG32(FAR2, 0x18)
+REG32(FAR3, 0x1c)
+REG32(FAR_SFR0, 0x20)
+ FIELD(FAR_SFR0, BLOCKTYPE, 20, 3)
+ FIELD(FAR_SFR0, FRAME_ADDR, 0, 20)
+REG32(FAR_SFR1, 0x24)
+REG32(FAR_SFR2, 0x28)
+REG32(FAR_SFR3, 0x2c)
+REG32(FDRI0, 0x40)
+REG32(FDRI1, 0x44)
+REG32(FDRI2, 0x48)
+REG32(FDRI3, 0x4c)
+REG32(FRCNT0, 0x50)
+ FIELD(FRCNT0, FRCNT, 0, 32)
+REG32(FRCNT1, 0x54)
+REG32(FRCNT2, 0x58)
+REG32(FRCNT3, 0x5c)
+REG32(CMD0, 0x60)
+ FIELD(CMD0, CMD, 0, 5)
+REG32(CMD1, 0x64)
+REG32(CMD2, 0x68)
+REG32(CMD3, 0x6c)
+REG32(CR_MASK0, 0x70)
+REG32(CR_MASK1, 0x74)
+REG32(CR_MASK2, 0x78)
+REG32(CR_MASK3, 0x7c)
+REG32(CTL0, 0x80)
+ FIELD(CTL, PER_FRAME_CRC, 0, 1)
+REG32(CTL1, 0x84)
+REG32(CTL2, 0x88)
+REG32(CTL3, 0x8c)
+REG32(CFRM_ISR0, 0x150)
+ FIELD(CFRM_ISR0, READ_BROADCAST_ERROR, 21, 1)
+ FIELD(CFRM_ISR0, CMD_MISSING_ERROR, 20, 1)
+ FIELD(CFRM_ISR0, RW_ROWOFF_ERROR, 19, 1)
+ FIELD(CFRM_ISR0, READ_REG_ADDR_ERROR, 18, 1)
+ FIELD(CFRM_ISR0, READ_BLK_TYPE_ERROR, 17, 1)
+ FIELD(CFRM_ISR0, READ_FRAME_ADDR_ERROR, 16, 1)
+ FIELD(CFRM_ISR0, WRITE_REG_ADDR_ERROR, 15, 1)
+ FIELD(CFRM_ISR0, WRITE_BLK_TYPE_ERROR, 13, 1)
+ FIELD(CFRM_ISR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
+ FIELD(CFRM_ISR0, MFW_OVERRUN_ERROR, 11, 1)
+ FIELD(CFRM_ISR0, FAR_FIFO_UNDERFLOW, 10, 1)
+ FIELD(CFRM_ISR0, FAR_FIFO_OVERFLOW, 9, 1)
+ FIELD(CFRM_ISR0, PER_FRAME_SEQ_ERROR, 8, 1)
+ FIELD(CFRM_ISR0, CRC_ERROR, 7, 1)
+ FIELD(CFRM_ISR0, WRITE_OVERRUN_ERROR, 6, 1)
+ FIELD(CFRM_ISR0, READ_OVERRUN_ERROR, 5, 1)
+ FIELD(CFRM_ISR0, CMD_INTERRUPT_ERROR, 4, 1)
+ FIELD(CFRM_ISR0, WRITE_INTERRUPT_ERROR, 3, 1)
+ FIELD(CFRM_ISR0, READ_INTERRUPT_ERROR, 2, 1)
+ FIELD(CFRM_ISR0, SEU_CRC_ERROR, 1, 1)
+ FIELD(CFRM_ISR0, SEU_ECC_ERROR, 0, 1)
+REG32(CFRM_ISR1, 0x154)
+REG32(CFRM_ISR2, 0x158)
+REG32(CFRM_ISR3, 0x15c)
+REG32(CFRM_IMR0, 0x160)
+ FIELD(CFRM_IMR0, READ_BROADCAST_ERROR, 21, 1)
+ FIELD(CFRM_IMR0, CMD_MISSING_ERROR, 20, 1)
+ FIELD(CFRM_IMR0, RW_ROWOFF_ERROR, 19, 1)
+ FIELD(CFRM_IMR0, READ_REG_ADDR_ERROR, 18, 1)
+ FIELD(CFRM_IMR0, READ_BLK_TYPE_ERROR, 17, 1)
+ FIELD(CFRM_IMR0, READ_FRAME_ADDR_ERROR, 16, 1)
+ FIELD(CFRM_IMR0, WRITE_REG_ADDR_ERROR, 15, 1)
+ FIELD(CFRM_IMR0, WRITE_BLK_TYPE_ERROR, 13, 1)
+ FIELD(CFRM_IMR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
+ FIELD(CFRM_IMR0, MFW_OVERRUN_ERROR, 11, 1)
+ FIELD(CFRM_IMR0, FAR_FIFO_UNDERFLOW, 10, 1)
+ FIELD(CFRM_IMR0, FAR_FIFO_OVERFLOW, 9, 1)
+ FIELD(CFRM_IMR0, PER_FRAME_SEQ_ERROR, 8, 1)
+ FIELD(CFRM_IMR0, CRC_ERROR, 7, 1)
+ FIELD(CFRM_IMR0, WRITE_OVERRUN_ERROR, 6, 1)
+ FIELD(CFRM_IMR0, READ_OVERRUN_ERROR, 5, 1)
+ FIELD(CFRM_IMR0, CMD_INTERRUPT_ERROR, 4, 1)
+ FIELD(CFRM_IMR0, WRITE_INTERRUPT_ERROR, 3, 1)
+ FIELD(CFRM_IMR0, READ_INTERRUPT_ERROR, 2, 1)
+ FIELD(CFRM_IMR0, SEU_CRC_ERROR, 1, 1)
+ FIELD(CFRM_IMR0, SEU_ECC_ERROR, 0, 1)
+REG32(CFRM_IMR1, 0x164)
+REG32(CFRM_IMR2, 0x168)
+REG32(CFRM_IMR3, 0x16c)
+REG32(CFRM_IER0, 0x170)
+ FIELD(CFRM_IER0, READ_BROADCAST_ERROR, 21, 1)
+ FIELD(CFRM_IER0, CMD_MISSING_ERROR, 20, 1)
+ FIELD(CFRM_IER0, RW_ROWOFF_ERROR, 19, 1)
+ FIELD(CFRM_IER0, READ_REG_ADDR_ERROR, 18, 1)
+ FIELD(CFRM_IER0, READ_BLK_TYPE_ERROR, 17, 1)
+ FIELD(CFRM_IER0, READ_FRAME_ADDR_ERROR, 16, 1)
+ FIELD(CFRM_IER0, WRITE_REG_ADDR_ERROR, 15, 1)
+ FIELD(CFRM_IER0, WRITE_BLK_TYPE_ERROR, 13, 1)
+ FIELD(CFRM_IER0, WRITE_FRAME_ADDR_ERROR, 12, 1)
+ FIELD(CFRM_IER0, MFW_OVERRUN_ERROR, 11, 1)
+ FIELD(CFRM_IER0, FAR_FIFO_UNDERFLOW, 10, 1)
+ FIELD(CFRM_IER0, FAR_FIFO_OVERFLOW, 9, 1)
+ FIELD(CFRM_IER0, PER_FRAME_SEQ_ERROR, 8, 1)
+ FIELD(CFRM_IER0, CRC_ERROR, 7, 1)
+ FIELD(CFRM_IER0, WRITE_OVERRUN_ERROR, 6, 1)
+ FIELD(CFRM_IER0, READ_OVERRUN_ERROR, 5, 1)
+ FIELD(CFRM_IER0, CMD_INTERRUPT_ERROR, 4, 1)
+ FIELD(CFRM_IER0, WRITE_INTERRUPT_ERROR, 3, 1)
+ FIELD(CFRM_IER0, READ_INTERRUPT_ERROR, 2, 1)
+ FIELD(CFRM_IER0, SEU_CRC_ERROR, 1, 1)
+ FIELD(CFRM_IER0, SEU_ECC_ERROR, 0, 1)
+REG32(CFRM_IER1, 0x174)
+REG32(CFRM_IER2, 0x178)
+REG32(CFRM_IER3, 0x17c)
+REG32(CFRM_IDR0, 0x180)
+ FIELD(CFRM_IDR0, READ_BROADCAST_ERROR, 21, 1)
+ FIELD(CFRM_IDR0, CMD_MISSING_ERROR, 20, 1)
+ FIELD(CFRM_IDR0, RW_ROWOFF_ERROR, 19, 1)
+ FIELD(CFRM_IDR0, READ_REG_ADDR_ERROR, 18, 1)
+ FIELD(CFRM_IDR0, READ_BLK_TYPE_ERROR, 17, 1)
+ FIELD(CFRM_IDR0, READ_FRAME_ADDR_ERROR, 16, 1)
+ FIELD(CFRM_IDR0, WRITE_REG_ADDR_ERROR, 15, 1)
+ FIELD(CFRM_IDR0, WRITE_BLK_TYPE_ERROR, 13, 1)
+ FIELD(CFRM_IDR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
+ FIELD(CFRM_IDR0, MFW_OVERRUN_ERROR, 11, 1)
+ FIELD(CFRM_IDR0, FAR_FIFO_UNDERFLOW, 10, 1)
+ FIELD(CFRM_IDR0, FAR_FIFO_OVERFLOW, 9, 1)
+ FIELD(CFRM_IDR0, PER_FRAME_SEQ_ERROR, 8, 1)
+ FIELD(CFRM_IDR0, CRC_ERROR, 7, 1)
+ FIELD(CFRM_IDR0, WRITE_OVERRUN_ERROR, 6, 1)
+ FIELD(CFRM_IDR0, READ_OVERRUN_ERROR, 5, 1)
+ FIELD(CFRM_IDR0, CMD_INTERRUPT_ERROR, 4, 1)
+ FIELD(CFRM_IDR0, WRITE_INTERRUPT_ERROR, 3, 1)
+ FIELD(CFRM_IDR0, READ_INTERRUPT_ERROR, 2, 1)
+ FIELD(CFRM_IDR0, SEU_CRC_ERROR, 1, 1)
+ FIELD(CFRM_IDR0, SEU_ECC_ERROR, 0, 1)
+REG32(CFRM_IDR1, 0x184)
+REG32(CFRM_IDR2, 0x188)
+REG32(CFRM_IDR3, 0x18c)
+REG32(CFRM_ITR0, 0x190)
+ FIELD(CFRM_ITR0, READ_BROADCAST_ERROR, 21, 1)
+ FIELD(CFRM_ITR0, CMD_MISSING_ERROR, 20, 1)
+ FIELD(CFRM_ITR0, RW_ROWOFF_ERROR, 19, 1)
+ FIELD(CFRM_ITR0, READ_REG_ADDR_ERROR, 18, 1)
+ FIELD(CFRM_ITR0, READ_BLK_TYPE_ERROR, 17, 1)
+ FIELD(CFRM_ITR0, READ_FRAME_ADDR_ERROR, 16, 1)
+ FIELD(CFRM_ITR0, WRITE_REG_ADDR_ERROR, 15, 1)
+ FIELD(CFRM_ITR0, WRITE_BLK_TYPE_ERROR, 13, 1)
+ FIELD(CFRM_ITR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
+ FIELD(CFRM_ITR0, MFW_OVERRUN_ERROR, 11, 1)
+ FIELD(CFRM_ITR0, FAR_FIFO_UNDERFLOW, 10, 1)
+ FIELD(CFRM_ITR0, FAR_FIFO_OVERFLOW, 9, 1)
+ FIELD(CFRM_ITR0, PER_FRAME_SEQ_ERROR, 8, 1)
+ FIELD(CFRM_ITR0, CRC_ERROR, 7, 1)
+ FIELD(CFRM_ITR0, WRITE_OVERRUN_ERROR, 6, 1)
+ FIELD(CFRM_ITR0, READ_OVERRUN_ERROR, 5, 1)
+ FIELD(CFRM_ITR0, CMD_INTERRUPT_ERROR, 4, 1)
+ FIELD(CFRM_ITR0, WRITE_INTERRUPT_ERROR, 3, 1)
+ FIELD(CFRM_ITR0, READ_INTERRUPT_ERROR, 2, 1)
+ FIELD(CFRM_ITR0, SEU_CRC_ERROR, 1, 1)
+ FIELD(CFRM_ITR0, SEU_ECC_ERROR, 0, 1)
+REG32(CFRM_ITR1, 0x194)
+REG32(CFRM_ITR2, 0x198)
+REG32(CFRM_ITR3, 0x19c)
+REG32(SEU_SYNDRM00, 0x1a0)
+REG32(SEU_SYNDRM01, 0x1a4)
+REG32(SEU_SYNDRM02, 0x1a8)
+REG32(SEU_SYNDRM03, 0x1ac)
+REG32(SEU_SYNDRM10, 0x1b0)
+REG32(SEU_SYNDRM11, 0x1b4)
+REG32(SEU_SYNDRM12, 0x1b8)
+REG32(SEU_SYNDRM13, 0x1bc)
+REG32(SEU_SYNDRM20, 0x1c0)
+REG32(SEU_SYNDRM21, 0x1c4)
+REG32(SEU_SYNDRM22, 0x1c8)
+REG32(SEU_SYNDRM23, 0x1cc)
+REG32(SEU_SYNDRM30, 0x1d0)
+REG32(SEU_SYNDRM31, 0x1d4)
+REG32(SEU_SYNDRM32, 0x1d8)
+REG32(SEU_SYNDRM33, 0x1dc)
+REG32(SEU_VIRTUAL_SYNDRM0, 0x1e0)
+REG32(SEU_VIRTUAL_SYNDRM1, 0x1e4)
+REG32(SEU_VIRTUAL_SYNDRM2, 0x1e8)
+REG32(SEU_VIRTUAL_SYNDRM3, 0x1ec)
+REG32(SEU_CRC0, 0x1f0)
+REG32(SEU_CRC1, 0x1f4)
+REG32(SEU_CRC2, 0x1f8)
+REG32(SEU_CRC3, 0x1fc)
+REG32(CFRAME_FAR_BOT0, 0x200)
+REG32(CFRAME_FAR_BOT1, 0x204)
+REG32(CFRAME_FAR_BOT2, 0x208)
+REG32(CFRAME_FAR_BOT3, 0x20c)
+REG32(CFRAME_FAR_TOP0, 0x210)
+REG32(CFRAME_FAR_TOP1, 0x214)
+REG32(CFRAME_FAR_TOP2, 0x218)
+REG32(CFRAME_FAR_TOP3, 0x21c)
+REG32(LAST_FRAME_BOT0, 0x220)
+ FIELD(LAST_FRAME_BOT0, BLOCKTYPE1_LAST_FRAME_LSB, 20, 12)
+ FIELD(LAST_FRAME_BOT0, BLOCKTYPE0_LAST_FRAME, 0, 20)
+REG32(LAST_FRAME_BOT1, 0x224)
+ FIELD(LAST_FRAME_BOT1, BLOCKTYPE3_LAST_FRAME_LSB, 28, 4)
+ FIELD(LAST_FRAME_BOT1, BLOCKTYPE2_LAST_FRAME, 8, 20)
+ FIELD(LAST_FRAME_BOT1, BLOCKTYPE1_LAST_FRAME_MSB, 0, 8)
+REG32(LAST_FRAME_BOT2, 0x228)
+ FIELD(LAST_FRAME_BOT2, BLOCKTYPE3_LAST_FRAME_MSB, 0, 16)
+REG32(LAST_FRAME_BOT3, 0x22c)
+REG32(LAST_FRAME_TOP0, 0x230)
+ FIELD(LAST_FRAME_TOP0, BLOCKTYPE5_LAST_FRAME_LSB, 20, 12)
+ FIELD(LAST_FRAME_TOP0, BLOCKTYPE4_LAST_FRAME, 0, 20)
+REG32(LAST_FRAME_TOP1, 0x234)
+ FIELD(LAST_FRAME_TOP1, BLOCKTYPE6_LAST_FRAME, 8, 20)
+ FIELD(LAST_FRAME_TOP1, BLOCKTYPE5_LAST_FRAME_MSB, 0, 8)
+REG32(LAST_FRAME_TOP2, 0x238)
+REG32(LAST_FRAME_TOP3, 0x23c)
+
+#define CFRAME_REG_R_MAX (R_LAST_FRAME_TOP3 + 1)
+
+#define FRAME_NUM_QWORDS 25
+#define FRAME_NUM_WORDS (FRAME_NUM_QWORDS * 4) /* 25 * 128 bits */
+
+typedef struct XlnxCFrame {
+ uint32_t addr;
+ uint32_t idx;
+ uint32_t data[FRAME_NUM_WORDS];
+} XlnxCFrame;
+
+struct XlnxVersalCFrameReg {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ MemoryRegion iomem_fdri;
+ qemu_irq irq_cfrm_imr;
+
+ /* 128-bit wfifo. */
+ uint32_t wfifo[4];
+
+ uint32_t regs[CFRAME_REG_R_MAX];
+ RegisterInfo regs_info[CFRAME_REG_R_MAX];
+
+ bool rowon;
+ bool wcfg;
+ bool rcfg;
+
+ GArray *cframes;
+ XlnxCFrame new_f;
+ uint32_t *cf_data;
+ uint32_t cf_dlen;
+
+ struct {
+ XlnxCfiIf *cfu_fdro;
+ uint32_t blktype_num_frames[7];
+ } cfg;
+ bool row_configured;
+};
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
2023-07-10 14:02 ` [PATCH v1 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Francisco Iglesias
@ 2023-08-03 14:01 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 14:01 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Introduce a model of Xilinx Versal's Configuration Frame controller
> (CFRAME_REG).
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> MAINTAINERS | 2 +
> hw/misc/meson.build | 1 +
> hw/misc/xlnx-versal-cframe-reg.c | 714 +++++++++++++++++++++++
> include/hw/misc/xlnx-versal-cframe-reg.h | 288 +++++++++
> 4 files changed, 1005 insertions(+)
> create mode 100644 hw/misc/xlnx-versal-cframe-reg.c
> create mode 100644 include/hw/misc/xlnx-versal-cframe-reg.h
>
> +#define KEYHOLE_STREAM_4K 0x1000
You could define this as (4 * KiB) which would then be more
clearly 4K.
> +
> +#define MAX_BLOCKTYPE 6
> +#define MAX_BLOCKTYPE_FRAMES 0xFFFFF
> +
> +enum {
> + CFRAME_CMD_WCFG = 1,
> + CFRAME_CMD_ROWON = 2,
> + CFRAME_CMD_ROWOFF = 3,
> + CFRAME_CMD_RCFG = 4,
> + CFRAME_CMD_DLPARK = 5
minor style nit -- leaving the trailing ',' on the last
item in an enum or similar means that the next person
to add another entry doesn't have to edit the previous
line to put the comma in.
> +};
> +static void cfrm_fdri_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(reg->opaque);
> +
> + if (s->row_configured && s->rowon && s->wcfg) {
> + XlnxCFrame *new_f = &s->new_f;
> +
> + new_f->data[new_f->idx++] = s->regs[R_FDRI0];
> + new_f->data[new_f->idx++] = s->regs[R_FDRI1];
> + new_f->data[new_f->idx++] = s->regs[R_FDRI2];
> + new_f->data[new_f->idx++] = s->regs[R_FDRI3];
> +
> + assert(new_f->idx <= FRAME_NUM_WORDS);
We should assert that we're not overrunning the array
*before* we write the data, not afterwards.
More generally, this kind of "we have a data array and
an index into it and we store stuff in at the index"
is prime territory for bugs resulting in array overruns.
If there's a way to write it that makes it clear that
that can't happen (esp. abstracting out what the operations
on the data structure are, documenting the invariants, etc)
then we should take it.
> +
> + if (new_f->idx == FRAME_NUM_WORDS) {
> + XlnxCFrame *cur_f;
> +
> + /* Include block type and frame address */
> + new_f->addr = extract32(s->regs[R_FAR0], 0, 23);
> +
> + cur_f = cframes_get_frame(s, new_f->addr);
> +
> + if (cur_f) {
> + /* Overwrite current frame */
> + cur_f[0] = new_f[0];
> + } else {
> + g_array_append_val(s->cframes, new_f[0]);
> + }
> +
> + cframe_incr_far(s);
> +
> + /* Clear out new_f */
> + memset(new_f, 0, sizeof(*new_f));
> + }
> + }
> +}
> +static int cframes_reg_pre_save(void *opaque)
> +{
> + XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(opaque);
> +
> + if (s->cframes->len) {
> + s->cf_data = (uint32_t *) s->cframes->data;
> + s->cf_dlen = s->cframes->len * g_array_get_element_size(s->cframes) / 4;
> + }
> + return 0;
> +}
> +
> +static int cframes_reg_post_load(void *opaque, int version_id)
> +{
> + XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(opaque);
> +
> + if (s->cf_dlen) {
> + uint32_t num_frames = s->cf_dlen /
> + (g_array_get_element_size(s->cframes) / 4);
> + g_array_append_vals(s->cframes, s->cf_data, num_frames);
> + }
> + return 0;
> +}
Same remarks here about handling of GArray vs VMSTATE ALLOC.
(Or we could implement a VMSTATE macro/support for GArrays,
I guess. That would arguably be neater.)
> +
> +static const VMStateDescription vmstate_cframe_reg = {
> + .name = TYPE_XLNX_VERSAL_CFRAME_REG,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .pre_save = cframes_reg_pre_save,
> + .post_load = cframes_reg_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFrameReg, 4),
> + VMSTATE_UINT32_ARRAY(regs, XlnxVersalCFrameReg, CFRAME_REG_R_MAX),
> + VMSTATE_BOOL(rowon, XlnxVersalCFrameReg),
> + VMSTATE_BOOL(wcfg, XlnxVersalCFrameReg),
> + VMSTATE_BOOL(rcfg, XlnxVersalCFrameReg),
> + VMSTATE_VARRAY_UINT32_ALLOC(cf_data, XlnxVersalCFrameReg, cf_dlen,
> + 0, vmstate_info_uint32, uint32_t),
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static Property cframe_regs_props[] = {
> + /* Kept for backwards compatibility */
Backwards compatibility with who? This is the first implementation
of this as far as upstream is concerned...
> + DEFINE_PROP_LINK("cfu", XlnxVersalCFrameReg, cfg.cfu_fdro,
> + TYPE_XLNX_CFI_IF, XlnxCfiIf *),
> + DEFINE_PROP_LINK("cfu-fdro", XlnxVersalCFrameReg, cfg.cfu_fdro,
> + TYPE_XLNX_CFI_IF, XlnxCfiIf *),
> + DEFINE_PROP_UINT32("blktype0-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[0], 0),
> + DEFINE_PROP_UINT32("blktype1-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[1], 0),
> + DEFINE_PROP_UINT32("blktype2-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[2], 0),
> + DEFINE_PROP_UINT32("blktype3-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[3], 0),
> + DEFINE_PROP_UINT32("blktype4-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[4], 0),
> + DEFINE_PROP_UINT32("blktype5-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[5], 0),
> + DEFINE_PROP_UINT32("blktype6-frames", XlnxVersalCFrameReg,
> + cfg.blktype_num_frames[6], 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
` (4 preceding siblings ...)
2023-07-10 14:02 ` [PATCH v1 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 14:04 ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR Francisco Iglesias
` (2 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
hw/misc/xlnx-versal-cframe-reg.c | 173 +++++++++++++++++++++++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2 files changed, 190 insertions(+)
diff --git a/hw/misc/xlnx-versal-cframe-reg.c b/hw/misc/xlnx-versal-cframe-reg.c
index 7e3420e14d..4f90eaa240 100644
--- a/hw/misc/xlnx-versal-cframe-reg.c
+++ b/hw/misc/xlnx-versal-cframe-reg.c
@@ -571,6 +571,104 @@ static const MemoryRegionOps cframe_reg_fdri_ops = {
},
};
+static uint64_t cframes_bcast_reg_read(void *opaque, hwaddr addr, unsigned size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+}
+
+static void cframes_bcast_reg_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
+ unsigned int idx;
+
+ /* 4 32bit words. */
+ idx = (addr >> 2) & 3;
+
+ s->wfifo[idx] = value;
+
+ /* Writing to the top word triggers the transmit onto CFI. */
+ if (idx == 3) {
+ uint32_t reg_addr = extract32(addr, 4, 6);
+ XlnxCfiPacket pkt = {
+ .reg_addr = reg_addr,
+ .data[0] = s->wfifo[0],
+ .data[1] = s->wfifo[1],
+ .data[2] = s->wfifo[2],
+ .data[3] = s->wfifo[3]
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
+ if (s->cfg.cframe[i]) {
+ xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
+ }
+ }
+
+ memset(s->wfifo, 0, 4 * sizeof(uint32_t));
+ }
+}
+
+static uint64_t cframes_bcast_fdri_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+}
+
+static void cframes_bcast_fdri_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
+ unsigned int idx;
+
+ /* 4 32bit words. */
+ idx = (addr >> 2) & 3;
+
+ s->wfifo[idx] = value;
+
+ /* Writing to the top word triggers the transmit onto CFI. */
+ if (idx == 3) {
+ XlnxCfiPacket pkt = {
+ .reg_addr = CFRAME_FDRI,
+ .data[0] = s->wfifo[0],
+ .data[1] = s->wfifo[1],
+ .data[2] = s->wfifo[2],
+ .data[3] = s->wfifo[3]
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
+ if (s->cfg.cframe[i]) {
+ xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
+ }
+ }
+
+ memset(s->wfifo, 0, 4 * sizeof(uint32_t));
+ }
+}
+
+static const MemoryRegionOps cframes_bcast_reg_reg_ops = {
+ .read = cframes_bcast_reg_read,
+ .write = cframes_bcast_reg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static const MemoryRegionOps cframes_bcast_reg_fdri_ops = {
+ .read = cframes_bcast_fdri_read,
+ .write = cframes_bcast_fdri_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
static void cframe_reg_realize(DeviceState *dev, Error **errp)
{
XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(dev);
@@ -680,6 +778,64 @@ static Property cframe_regs_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void cframe_bcast_reg_init(Object *obj)
+{
+ XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->iomem_reg, obj, &cframes_bcast_reg_reg_ops, s,
+ TYPE_XLNX_VERSAL_CFRAME_BCAST_REG, KEYHOLE_STREAM_4K);
+ memory_region_init_io(&s->iomem_fdri, obj, &cframes_bcast_reg_fdri_ops, s,
+ TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "-fdri",
+ KEYHOLE_STREAM_4K);
+ sysbus_init_mmio(sbd, &s->iomem_reg);
+ sysbus_init_mmio(sbd, &s->iomem_fdri);
+}
+
+static const VMStateDescription vmstate_cframe_bcast_reg = {
+ .name = TYPE_XLNX_VERSAL_CFRAME_BCAST_REG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(wfifo, XlnxVersalCFrameBcastReg, 4),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property cframe_bcast_regs_props[] = {
+ DEFINE_PROP_LINK("cframe0", XlnxVersalCFrameBcastReg, cfg.cframe[0],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe1", XlnxVersalCFrameBcastReg, cfg.cframe[1],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe2", XlnxVersalCFrameBcastReg, cfg.cframe[2],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe3", XlnxVersalCFrameBcastReg, cfg.cframe[3],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe4", XlnxVersalCFrameBcastReg, cfg.cframe[4],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe5", XlnxVersalCFrameBcastReg, cfg.cframe[5],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe6", XlnxVersalCFrameBcastReg, cfg.cframe[6],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe7", XlnxVersalCFrameBcastReg, cfg.cframe[7],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe8", XlnxVersalCFrameBcastReg, cfg.cframe[8],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe9", XlnxVersalCFrameBcastReg, cfg.cframe[9],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe10", XlnxVersalCFrameBcastReg, cfg.cframe[10],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe11", XlnxVersalCFrameBcastReg, cfg.cframe[11],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe12", XlnxVersalCFrameBcastReg, cfg.cframe[12],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe13", XlnxVersalCFrameBcastReg, cfg.cframe[13],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_LINK("cframe14", XlnxVersalCFrameBcastReg, cfg.cframe[14],
+ TYPE_XLNX_CFI_IF, XlnxCfiIf *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void cframe_reg_class_init(ObjectClass *klass, void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -694,6 +850,14 @@ static void cframe_reg_class_init(ObjectClass *klass, void *data)
xcic->cfi_transfer_packet = cframe_reg_cfi_transfer_packet;
}
+static void cframe_bcast_reg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_cframe_bcast_reg;
+ device_class_set_props(dc, cframe_bcast_regs_props);
+}
+
static const TypeInfo cframe_reg_info = {
.name = TYPE_XLNX_VERSAL_CFRAME_REG,
.parent = TYPE_SYS_BUS_DEVICE,
@@ -706,9 +870,18 @@ static const TypeInfo cframe_reg_info = {
}
};
+static const TypeInfo cframe_bcast_reg_info = {
+ .name = TYPE_XLNX_VERSAL_CFRAME_BCAST_REG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalCFrameBcastReg),
+ .class_init = cframe_bcast_reg_class_init,
+ .instance_init = cframe_bcast_reg_init,
+};
+
static void cframe_reg_register_types(void)
{
type_register_static(&cframe_reg_info);
+ type_register_static(&cframe_bcast_reg_info);
}
type_init(cframe_reg_register_types)
diff --git a/include/hw/misc/xlnx-versal-cframe-reg.h b/include/hw/misc/xlnx-versal-cframe-reg.h
index 07dd9ed3e4..c98d5d84f9 100644
--- a/include/hw/misc/xlnx-versal-cframe-reg.h
+++ b/include/hw/misc/xlnx-versal-cframe-reg.h
@@ -24,6 +24,10 @@
#define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx,cframe-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameReg, XLNX_VERSAL_CFRAME_REG)
+#define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameBcastReg,
+ XLNX_VERSAL_CFRAME_BCAST_REG)
+
/*
* The registers in this module are 128 bits wide but it is ok to write
* and read them through 4 sequential 32 bit accesses (address[3:2] = 0,
@@ -285,4 +289,17 @@ struct XlnxVersalCFrameReg {
bool row_configured;
};
+struct XlnxVersalCFrameBcastReg {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem_reg;
+ MemoryRegion iomem_fdri;
+
+ /* 128-bit wfifo. */
+ uint32_t wfifo[4];
+
+ struct {
+ XlnxCfiIf *cframe[15];
+ } cfg;
+};
+
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
2023-07-10 14:02 ` [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Francisco Iglesias
@ 2023-08-03 14:04 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 14:04 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Introduce a model of Xilinx Versal's Configuration Frame broadcast
> controller (CFRAME_BCAST_REG).
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> hw/misc/xlnx-versal-cframe-reg.c | 173 +++++++++++++++++++++++
> include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
> 2 files changed, 190 insertions(+)
Missing reset again.
> +static uint64_t cframes_bcast_reg_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
> + HWADDR_PRIx "\n", __func__, addr);
> + return 0;
> +}
> +
> +static void cframes_bcast_reg_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
> + unsigned int idx;
> +
> + /* 4 32bit words. */
> + idx = (addr >> 2) & 3;
> +
> + s->wfifo[idx] = value;
> +
> + /* Writing to the top word triggers the transmit onto CFI. */
> + if (idx == 3) {
> + uint32_t reg_addr = extract32(addr, 4, 6);
> + XlnxCfiPacket pkt = {
> + .reg_addr = reg_addr,
> + .data[0] = s->wfifo[0],
> + .data[1] = s->wfifo[1],
> + .data[2] = s->wfifo[2],
> + .data[3] = s->wfifo[3]
> + };
> +
> + for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
> + if (s->cfg.cframe[i]) {
> + xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
> + }
> + }
> +
> + memset(s->wfifo, 0, 4 * sizeof(uint32_t));
> + }
> +}
> +static void cframes_bcast_fdri_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
> + unsigned int idx;
> +
> + /* 4 32bit words. */
> + idx = (addr >> 2) & 3;
> +
> + s->wfifo[idx] = value;
> +
> + /* Writing to the top word triggers the transmit onto CFI. */
> + if (idx == 3) {
> + XlnxCfiPacket pkt = {
> + .reg_addr = CFRAME_FDRI,
> + .data[0] = s->wfifo[0],
> + .data[1] = s->wfifo[1],
> + .data[2] = s->wfifo[2],
> + .data[3] = s->wfifo[3]
> + };
> +
> + for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
> + if (s->cfg.cframe[i]) {
> + xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
> + }
> + }
> +
> + memset(s->wfifo, 0, 4 * sizeof(uint32_t));
> + }
> +}
I feel like I've seen this code structure in several patches:
opportunity to share code ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
` (5 preceding siblings ...)
2023-07-10 14:02 ` [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 13:50 ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Francisco Iglesias
2023-07-12 12:20 ` [PATCH v1 0/8] Xilinx Versal CFI support Edgar E. Iglesias
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
hw/arm/xlnx-versal.c | 42 ++++++++++++++++++++++++++++++++++++
include/hw/arm/xlnx-versal.h | 16 ++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 60bf5fe657..3f4b4b1560 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -570,6 +570,47 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
}
+static void versal_create_cfu(Versal *s, qemu_irq *pic)
+{
+ SysBusDevice *sbd;
+
+ /* CFU FDRO */
+ object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro,
+ TYPE_XLNX_VERSAL_CFU_FDRO);
+ sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro);
+
+ sysbus_realize(sbd, &error_fatal);
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO,
+ sysbus_mmio_get_region(sbd, 0));
+
+ /* CFU APB */
+ object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb,
+ TYPE_XLNX_VERSAL_CFU_APB);
+ sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb);
+
+ sysbus_realize(sbd, &error_fatal);
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB,
+ sysbus_mmio_get_region(sbd, 0));
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM,
+ sysbus_mmio_get_region(sbd, 1));
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2,
+ sysbus_mmio_get_region(sbd, 2));
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]);
+
+ /* CFU SFR */
+ object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr,
+ TYPE_XLNX_VERSAL_CFU_SFR);
+
+ sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr);
+
+ object_property_set_link(OBJECT(&s->pmc.cfu_sfr),
+ "cfu", OBJECT(&s->pmc.cfu_apb), &error_abort);
+
+ sysbus_realize(sbd, &error_fatal);
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR,
+ sysbus_mmio_get_region(sbd, 0));
+}
+
static void versal_create_crl(Versal *s, qemu_irq *pic)
{
SysBusDevice *sbd;
@@ -763,6 +804,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_pmc_iou_slcr(s, pic);
versal_create_ospi(s, pic);
versal_create_crl(s, pic);
+ versal_create_cfu(s, pic);
versal_map_ddr(s);
versal_unimp(s);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 39ee31185c..29b9c60301 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -32,6 +32,7 @@
#include "hw/misc/xlnx-versal-crl.h"
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#include "hw/net/xlnx-versal-canfd.h"
+#include "hw/misc/xlnx-versal-cfu.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -117,6 +118,9 @@ struct Versal {
XlnxEFuse efuse;
XlnxVersalEFuseCtrl efuse_ctrl;
XlnxVersalEFuseCache efuse_cache;
+ XlnxVersalCFUAPB cfu_apb;
+ XlnxVersalCFUFDRO cfu_fdro;
+ XlnxVersalCFUSFR cfu_sfr;
OrIRQState apb_irq_orgate;
} pmc;
@@ -147,6 +151,7 @@ struct Versal {
#define VERSAL_GEM1_WAKE_IRQ_0 59
#define VERSAL_ADMA_IRQ_0 60
#define VERSAL_XRAM_IRQ_0 79
+#define VERSAL_CFU_IRQ_0 120
#define VERSAL_PMC_APB_IRQ 121
#define VERSAL_OSPI_IRQ 124
#define VERSAL_SD0_IRQ_0 126
@@ -240,6 +245,17 @@ struct Versal {
#define MM_PMC_EFUSE_CACHE 0xf1250000
#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
+#define MM_PMC_CFU_APB 0xf12b0000
+#define MM_PMC_CFU_APB_SIZE 0x10000
+#define MM_PMC_CFU_STREAM 0xf12c0000
+#define MM_PMC_CFU_STREAM_SIZE 0x1000
+#define MM_PMC_CFU_SFR 0xf12c1000
+#define MM_PMC_CFU_SFR_SIZE 0x1000
+#define MM_PMC_CFU_FDRO 0xf12c2000
+#define MM_PMC_CFU_FDRO_SIZE 0x1000
+#define MM_PMC_CFU_STREAM_2 0xf1f80000
+#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
+
#define MM_PMC_CRP 0xf1260000U
#define MM_PMC_CRP_SIZE 0x10000
#define MM_PMC_RTC 0xf12a0000
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
2023-07-10 14:02 ` [PATCH v1 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR Francisco Iglesias
@ 2023-08-03 13:50 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 13:50 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
> the Versal machine.
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> hw/arm/xlnx-versal.c | 42 ++++++++++++++++++++++++++++++++++++
> include/hw/arm/xlnx-versal.h | 16 ++++++++++++++
> 2 files changed, 58 insertions(+)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
` (6 preceding siblings ...)
2023-07-10 14:02 ` [PATCH v1 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR Francisco Iglesias
@ 2023-07-10 14:02 ` Francisco Iglesias
2023-08-03 13:52 ` Peter Maydell
2023-07-12 12:20 ` [PATCH v1 0/8] Xilinx Versal CFI support Edgar E. Iglesias
8 siblings, 1 reply; 19+ messages in thread
From: Francisco Iglesias @ 2023-07-10 14:02 UTC (permalink / raw)
To: qemu-devel
Cc: frasse.iglesias, alistair, edgar.iglesias, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
hw/arm/xlnx-versal.c | 116 ++++++++++++++++++++++++++++++++++-
include/hw/arm/xlnx-versal.h | 69 +++++++++++++++++++++
2 files changed, 184 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 3f4b4b1560..9cd3c7218e 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -27,7 +27,7 @@
#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
#define GEM_REVISION 0x40070106
-#define VERSAL_NUM_PMC_APB_IRQS 3
+#define VERSAL_NUM_PMC_APB_IRQS 18
#define NUM_OSPI_IRQ_LINES 3
static void versal_create_apu_cpus(Versal *s)
@@ -341,6 +341,7 @@ static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
* - RTC
* - BBRAM
* - PMC SLCR
+ * - CFRAME regs (input 3 - 17 to the orgate)
*/
object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
&s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
@@ -573,6 +574,42 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
static void versal_create_cfu(Versal *s, qemu_irq *pic)
{
SysBusDevice *sbd;
+ DeviceState *dev;
+ int i;
+ const struct {
+ uint64_t reg_base;
+ uint64_t fdri_base;
+ } cframe_addr[] = {
+ { MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI },
+ { MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI },
+ { MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI },
+ { MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI },
+ { MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI },
+ { MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI },
+ { MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI },
+ { MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI },
+ { MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI },
+ { MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI },
+ { MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI },
+ { MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI },
+ { MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI },
+ { MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI },
+ { MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI },
+ };
+ const struct {
+ uint32_t blktype0_frames;
+ uint32_t blktype1_frames;
+ uint32_t blktype2_frames;
+ uint32_t blktype3_frames;
+ uint32_t blktype4_frames;
+ uint32_t blktype5_frames;
+ uint32_t blktype6_frames;
+ } cframe_cfg[] = {
+ [0] = { 34111, 3528, 12800, 11, 5, 1, 1 },
+ [1] = { 38498, 3841, 15361, 13, 7, 3, 1 },
+ [2] = { 38498, 3841, 15361, 13, 7, 3, 1 },
+ [3] = { 38498, 3841, 15361, 13, 7, 3, 1 },
+ };
/* CFU FDRO */
object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro,
@@ -583,10 +620,87 @@ static void versal_create_cfu(Versal *s, qemu_irq *pic)
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO,
sysbus_mmio_get_region(sbd, 0));
+ /* CFRAME REG */
+ for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
+ char *name = g_strdup_printf("cframe%d", i);
+
+ object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i],
+ TYPE_XLNX_VERSAL_CFRAME_REG);
+
+ sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]);
+ dev = DEVICE(&s->pmc.cframe[i]);
+
+ if (i < ARRAY_SIZE(cframe_cfg)) {
+ object_property_set_int(OBJECT(dev), "blktype0-frames",
+ cframe_cfg[i].blktype0_frames,
+ &error_abort);
+ object_property_set_int(OBJECT(dev), "blktype1-frames",
+ cframe_cfg[i].blktype1_frames,
+ &error_abort);
+ object_property_set_int(OBJECT(dev), "blktype2-frames",
+ cframe_cfg[i].blktype2_frames,
+ &error_abort);
+ object_property_set_int(OBJECT(dev), "blktype3-frames",
+ cframe_cfg[i].blktype3_frames,
+ &error_abort);
+ object_property_set_int(OBJECT(dev), "blktype4-frames",
+ cframe_cfg[i].blktype4_frames,
+ &error_abort);
+ object_property_set_int(OBJECT(dev), "blktype5-frames",
+ cframe_cfg[i].blktype5_frames,
+ &error_abort);
+ object_property_set_int(OBJECT(dev), "blktype6-frames",
+ cframe_cfg[i].blktype6_frames,
+ &error_abort);
+ }
+ object_property_set_link(OBJECT(dev), "cfu-fdro",
+ OBJECT(&s->pmc.cfu_fdro), &error_fatal);
+
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base,
+ sysbus_mmio_get_region(sbd, 0));
+ memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base,
+ sysbus_mmio_get_region(sbd, 1));
+ sysbus_connect_irq(sbd, 0,
+ qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate),
+ 3 + i));
+ g_free(name);
+ }
+
+ /* CFRAME BCAST */
+ object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast,
+ TYPE_XLNX_VERSAL_CFRAME_BCAST_REG);
+
+ sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast);
+ dev = DEVICE(&s->pmc.cframe_bcast);
+
+ for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
+ char *propname = g_strdup_printf("cframe%d", i);
+ object_property_set_link(OBJECT(dev), propname,
+ OBJECT(&s->pmc.cframe[i]), &error_fatal);
+ g_free(propname);
+ }
+
+ sysbus_realize(sbd, &error_fatal);
+
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG,
+ sysbus_mmio_get_region(sbd, 0));
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI,
+ sysbus_mmio_get_region(sbd, 1));
+
/* CFU APB */
object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb,
TYPE_XLNX_VERSAL_CFU_APB);
sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb);
+ dev = DEVICE(&s->pmc.cfu_apb);
+
+ for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
+ char *propname = g_strdup_printf("cframe%d", i);
+ object_property_set_link(OBJECT(dev), propname,
+ OBJECT(&s->pmc.cframe[i]), &error_fatal);
+ g_free(propname);
+ }
sysbus_realize(sbd, &error_fatal);
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB,
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 29b9c60301..7b419f88c2 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -33,6 +33,7 @@
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/misc/xlnx-versal-cfu.h"
+#include "hw/misc/xlnx-versal-cframe-reg.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -47,6 +48,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
#define XLNX_VERSAL_NR_IRQS 192
#define XLNX_VERSAL_NR_CANFD 2
#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
+#define XLNX_VERSAL_NR_CFRAME 15
struct Versal {
/*< private >*/
@@ -121,6 +123,8 @@ struct Versal {
XlnxVersalCFUAPB cfu_apb;
XlnxVersalCFUFDRO cfu_fdro;
XlnxVersalCFUSFR cfu_sfr;
+ XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
+ XlnxVersalCFrameBcastReg cframe_bcast;
OrIRQState apb_irq_orgate;
} pmc;
@@ -256,6 +260,71 @@ struct Versal {
#define MM_PMC_CFU_STREAM_2 0xf1f80000
#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
+#define MM_PMC_CFRAME0_REG 0xf12d0000
+#define MM_PMC_CFRAME0_REG_SIZE 0x1000
+#define MM_PMC_CFRAME0_FDRI 0xf12d1000
+#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME1_REG 0xf12d2000
+#define MM_PMC_CFRAME1_REG_SIZE 0x1000
+#define MM_PMC_CFRAME1_FDRI 0xf12d3000
+#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME2_REG 0xf12d4000
+#define MM_PMC_CFRAME2_REG_SIZE 0x1000
+#define MM_PMC_CFRAME2_FDRI 0xf12d5000
+#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME3_REG 0xf12d6000
+#define MM_PMC_CFRAME3_REG_SIZE 0x1000
+#define MM_PMC_CFRAME3_FDRI 0xf12d7000
+#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME4_REG 0xf12d8000
+#define MM_PMC_CFRAME4_REG_SIZE 0x1000
+#define MM_PMC_CFRAME4_FDRI 0xf12d9000
+#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME5_REG 0xf12da000
+#define MM_PMC_CFRAME5_REG_SIZE 0x1000
+#define MM_PMC_CFRAME5_FDRI 0xf12db000
+#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME6_REG 0xf12dc000
+#define MM_PMC_CFRAME6_REG_SIZE 0x1000
+#define MM_PMC_CFRAME6_FDRI 0xf12dd000
+#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME7_REG 0xf12de000
+#define MM_PMC_CFRAME7_REG_SIZE 0x1000
+#define MM_PMC_CFRAME7_FDRI 0xf12df000
+#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME8_REG 0xf12e0000
+#define MM_PMC_CFRAME8_REG_SIZE 0x1000
+#define MM_PMC_CFRAME8_FDRI 0xf12e1000
+#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME9_REG 0xf12e2000
+#define MM_PMC_CFRAME9_REG_SIZE 0x1000
+#define MM_PMC_CFRAME9_FDRI 0xf12e3000
+#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME10_REG 0xf12e4000
+#define MM_PMC_CFRAME10_REG_SIZE 0x1000
+#define MM_PMC_CFRAME10_FDRI 0xf12e5000
+#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME11_REG 0xf12e6000
+#define MM_PMC_CFRAME11_REG_SIZE 0x1000
+#define MM_PMC_CFRAME11_FDRI 0xf12e7000
+#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME12_REG 0xf12e8000
+#define MM_PMC_CFRAME12_REG_SIZE 0x1000
+#define MM_PMC_CFRAME12_FDRI 0xf12e9000
+#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME13_REG 0xf12ea000
+#define MM_PMC_CFRAME13_REG_SIZE 0x1000
+#define MM_PMC_CFRAME13_FDRI 0xf12eb000
+#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME14_REG 0xf12ec000
+#define MM_PMC_CFRAME14_REG_SIZE 0x1000
+#define MM_PMC_CFRAME14_FDRI 0xf12ed000
+#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
+#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
+#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
+#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
+#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
+
#define MM_PMC_CRP 0xf1260000U
#define MM_PMC_CRP_SIZE 0x10000
#define MM_PMC_RTC 0xf12a0000
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v1 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
2023-07-10 14:02 ` [PATCH v1 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Francisco Iglesias
@ 2023-08-03 13:52 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2023-08-03 13:52 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, edgar.iglesias, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Connect the Configuration Frame controller (CFRAME_REG) and the
> Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
> Versal machine.
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> + /* CFRAME REG */
> + for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
> + char *name = g_strdup_printf("cframe%d", i);
> +
> + object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i],
> + TYPE_XLNX_VERSAL_CFRAME_REG);
[...]
> + g_free(name);
g_autofree is nicer than this kind of explicit free, I think
(here and below)
> + }
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v1 0/8] Xilinx Versal CFI support
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
` (7 preceding siblings ...)
2023-07-10 14:02 ` [PATCH v1 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Francisco Iglesias
@ 2023-07-12 12:20 ` Edgar E. Iglesias
8 siblings, 0 replies; 19+ messages in thread
From: Edgar E. Iglesias @ 2023-07-12 12:20 UTC (permalink / raw)
To: Francisco Iglesias
Cc: qemu-devel, frasse.iglesias, alistair, peter.maydell, fkonrad,
sai.pavan.boddu, tong.ho, vikram.garhwal
[-- Attachment #1: Type: text/plain, Size: 2577 bytes --]
On Mon, Jul 10, 2023 at 4:02 PM Francisco Iglesias <
francisco.iglesias@amd.com> wrote:
> Hi,
>
> This series adds support for the Configuration Frame Unit (CFU) and the
> Configuration Frame controllers (CFRAME) to the Xilinx Versal machine
> ([1], chapter 21) for emulaing bitstream loading and readback.
>
> The series starts by introducing the Xilinx CFI interface that is
> thereafter used by the Xilinx CFU components, the Xilinx CFRAME and Xilinx
> CFRAME broadcast models for transfering CFI packets between each other.
> Thereafter a model of the CFU_APB, CFU_FDRO and CFU_SFR are introduced and
> also models of the CFRAME controller and CFRAME broadcast controller.
>
> The series thereafter ends with connecting the models to Xilinx Versal
> machine.
>
I just had a quick look and the series LGTM!
Acked-by: Edgar E. Iglesias <edgar@zeroasic.com>
>
> Best regards,
> Francisco Iglesias
>
> References:
> [1]
> https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PSM-Local-Registers
>
>
> Francisco Iglesias (8):
> hw/misc: Introduce the Xilinx CFI interface
> hw/misc: Introduce a model of Xilinx Versal's CFU_APB
> hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
> hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
> hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
> hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
> hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
> hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
>
> MAINTAINERS | 10 +
> hw/arm/xlnx-versal.c | 158 +++-
> hw/misc/meson.build | 3 +
> hw/misc/xlnx-cfi-if.c | 34 +
> hw/misc/xlnx-versal-cframe-reg.c | 887 +++++++++++++++++++++++
> hw/misc/xlnx-versal-cfu.c | 566 +++++++++++++++
> include/hw/arm/xlnx-versal.h | 85 +++
> include/hw/misc/xlnx-cfi-if.h | 59 ++
> include/hw/misc/xlnx-versal-cframe-reg.h | 305 ++++++++
> include/hw/misc/xlnx-versal-cfu.h | 238 ++++++
> 10 files changed, 2344 insertions(+), 1 deletion(-)
> create mode 100644 hw/misc/xlnx-cfi-if.c
> create mode 100644 hw/misc/xlnx-versal-cframe-reg.c
> create mode 100644 hw/misc/xlnx-versal-cfu.c
> create mode 100644 include/hw/misc/xlnx-cfi-if.h
> create mode 100644 include/hw/misc/xlnx-versal-cframe-reg.h
> create mode 100644 include/hw/misc/xlnx-versal-cfu.h
>
> --
> 2.34.1
>
>
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^ permalink raw reply [flat|nested] 19+ messages in thread