From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl0Vw-0005hS-Pv for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:55:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rl0Vn-00076H-9Z for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:55:00 -0500 Received: from mail-qw0-f45.google.com ([209.85.216.45]:61706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl0Vn-00076C-7H for qemu-devel@nongnu.org; Wed, 11 Jan 2012 10:54:51 -0500 Received: by qadc10 with SMTP id c10so2279665qad.4 for ; Wed, 11 Jan 2012 07:54:50 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1326295570-10060-3-git-send-email-mark.langsdorf@calxeda.com> References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com> <1326295570-10060-1-git-send-email-mark.langsdorf@calxeda.com> <1326295570-10060-3-git-send-email-mark.langsdorf@calxeda.com> Date: Wed, 11 Jan 2012 15:54:50 +0000 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Langsdorf Cc: i.mitsyanko@gmail.com, edgar.iglesias@gmail.com, qemu-devel@nongnu.org, afaerber@suse.de On 11 January 2012 15:26, Mark Langsdorf wrote= : > Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020, > and create a configurable property for each defaulting to 96 and 64 > (respectively) so that device modelers can set the value appropriately > for their SoC. Other ARM processors also set their maximum number of > used IRQs appropriately. > > Set the maximum theoretically number of GIC interrupts to 1020 and This patch has lost the typo fix ("theoretical") that was in the last version. I wouldn't bother mentioning this if not for: > +static SysBusDeviceInfo armv7m_nvic_priv_info =3D { > + =C2=A0 =C2=A0.init =3D armv7m_nvic_init, > + =C2=A0 =C2=A0.qdev.name =C2=A0=3D "armv7m_nvic", > + =C2=A0 =C2=A0.qdev.size =C2=A0=3D sizeof(nvic_state), > + =C2=A0 =C2=A0.qdev.vmsd =C2=A0=3D &vmstate_nvic, > + =C2=A0 =C2=A0.qdev.props =3D (Property[]) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* The ARM v7m may have anything from 0 to 4= 96 external interrupt > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 * IRQ lines. We default to 64 external and = 32 internal > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 * Other boards may differ and should set th= is property appropriately. > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 */ This is still wrong: from my comments on v5 of this patch: This comment shouldn't talk about the 32 internal lines, as they are an implementation detail of arm_gic.c, not architectural (unlike the A profile GIC internal interrupt lines). /* The ARM v7m may have anything from 0 to 496 external interrupt * IRQ lines. We default to 64. Other boards may differ and should * set this property appropriately. */ -- PMM