Re: [Qemu-devel] [PATCH v1 1/1] target-arm: helper.c: RAZ REVIDR cp register

[Peter Maydell <peter.maydell@linaro.org>]

On 23 April 2013 03:08,  <peter.crosthwaite@xilinx.com> wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Guests should be able to read REVIDR without suffering an abort. Just
> RAZ the REVIDR register.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
>
>  target-arm/helper.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index fd055e8..e655c74 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1187,6 +1187,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>              { .name = "TLBTR",
>                .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
>                .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> +            /* RAZ the REVIDR register */
> +            { .name = "REVIDR",
> +              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 6,
> +              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
>              /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
>              { .name = "DUMMY",
>                .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,

REVIDR is v7 only, so I don't think this is the right place to define it.
(It's also IMPDEF whether it exists or whether it's an alias for MIDR;
A7, A9 and A15 have a REVIDR, A5 and A8 don't.)

I suggest doing what we do for the MPIDR: define a feature bit
and a one-entry cp_reginfo for it.

(We don't implement the documented behaviour that unallocated
entries in c0,c0,0,X should read the MIDR, so I wouldn't worry
about that.)

thanks
-- PMM