Re: [Qemu-devel] [PATCH v4 00/21] More fully implement ARM PMUv3

[Peter Maydell <peter.maydell@linaro.org>]

On 17 April 2018 at 21:37, Aaron Lindsay <alindsay@codeaurora.org> wrote:
> The ARM PMU implementation currently contains a basic cycle counter, but it is
> often useful to gather counts of other events and filter them based on
> execution mode. These patches flesh out the implementations of various PMU
> registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to
> represent arbitrary counter types, implement mode filtering, send interrupts on
> counter overflow, and add instruction, cycle, and software increment events.
>
> Notable changes since v3:
>
> * Detect counter overflow and send interrupts accordingly (adds a 'shadow' copy
>   of both PMCCNTR and general-purpose counters, possibly/probably Doing It
>   Wrong)
> * Update counter filtering code to more closely resemble the ARM documentation
>   in form and functionality
> * Don't mix EL change hooks and KVM
> * Don't call gen_io_start/end if not actually using icount
> * Reorganized a few of the patches to more logically group changes
> * Clarify and otherwise improve a few comments
> * There are also a number of less significant changes scattered around

In the interests of cutting down the size of this patchset for
future rounds, I'm going to apply these patches to target-arm.next:

> 1  target/arm: Check PMCNTEN for whether PMCCNTR is enabled
> 2  target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
> 4  target/arm: Mask PMU register writes based on PMCR_EL0.N
> 5  target/arm: Fetch GICv3 state directly from CPUARMState
> 6  target/arm: Support multiple EL change hooks
> 7  target/arm: Add pre-EL change hooks
> 8  target/arm: Allow EL change hooks to do IO
> 9  target/arm: Fix bitmask for PMCCFILTR writes
> 12 target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide

thanks
-- PMM