Re: [PATCH] target/arm: align exposed ID registers with Linux

[Peter Maydell <peter.maydell@linaro.org>]

On Tue, 22 Nov 2022 at 03:05, Zhuojia Shen <chaosdefinition@hotmail.com> wrote:
>
> In CPUID registers exposed to userspace, some registers were missing
> and some fields were not exposed.  This patch aligns exposed ID
> registers and their fields with what Linux exposes currently.
>
> Specifically, the following new ID registers/fields are exposed to
> userspace:

These changes don't quite seem to line up with what the kernel
documents that it exposes:
https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.rst

> ID_AA64PFR1_EL1.BT:       bits 3-0
> ID_AA64PFR1_EL1.MTE:      bits 11-8
> ID_AA64PFR1_EL1.SME:      bits 27-24

.SME not listed as exposed.

> ID_AA64SMFR0_EL1.F32F32:  bit 32
> ID_AA64SMFR0_EL1.B16F32:  bit 34
> ID_AA64SMFR0_EL1.F16F32:  bit 35
> ID_AA64SMFR0_EL1.I8I32:   bits 39-36
> ID_AA64SMFR0_EL1.F64F64:  bit 48
> ID_AA64SMFR0_EL1.I16I64:  bits 55-52
> ID_AA64SMFR0_EL1.FA64:    bit 63

This register not listed as exposed.

> ID_AA64ISAR2_EL1.WFxT:    bits 3-0
> ID_AA64ISAR2_EL1.RPRES:   bits 7-4
> ID_AA64ISAR2_EL1.GPA3:    bits 11-8
> ID_AA64ISAR2_EL1.APA3:    bits 15-12

GPA3 and APA3 not listed as exposed.

thanks
-- PMM