From: Peter Maydell <peter.maydell@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages
Date: Tue, 25 May 2021 15:32:31 +0100 [thread overview]
Message-ID: <CAFEAcA863+SFfx8bV-zpw+ZUNAQsSJt_Gm3OA7i83dhPCviRaw@mail.gmail.com> (raw)
In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org>
On Sun, 9 May 2021 at 16:20, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Richard,
>
> I tried to make sense of the multiple changes in your patch
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg805595.html
> by splitting it in multiple trivial changes. At least this way
> it is easier to me to follow / review what you did.
>
> The original patch description was:
>
> Add tlb_flush interface for a range of pages.
> Call these tlb_flush_range_by_mmuidx*.
> Rewrite the_flush_page_bits_by_mmuidx* to use the new
> functions, passing in TARGET_PAGE_SIZE for length.
>
> If you find it useful, fill free to take / respin / reorder this
> series, improving descriptions. Last patch certainly deserves a
> better description ;)
Thanks very much for splitting this patch up -- it made it
a lot easier to review. I've added the commit messages
Richard has sent, moved the last patch to earlier in the
series, and applied the whole lot to target-arm.next.
-- PMM
next prev parent reply other threads:[~2021-05-25 14:35 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-09 15:16 [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages Philippe Mathieu-Daudé
2021-05-09 15:16 ` [PATCH 1/9] accel/tcg: Replace g_new() + memcpy() by g_memdup() Philippe Mathieu-Daudé
2021-05-25 13:31 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 2/9] accel/tcg: Pass length argument to tlb_flush_range_locked() Philippe Mathieu-Daudé
2021-05-09 15:16 ` [PATCH 3/9] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData Philippe Mathieu-Daudé
2021-05-25 13:38 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 4/9] accel/tcg: Add tlb_flush_range_by_mmuidx() Philippe Mathieu-Daudé
2021-05-25 13:42 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 5/9] accel/tcg: Add tlb_flush_page_bits_by_mmuidx_all_cpus() Philippe Mathieu-Daudé
2021-05-25 13:45 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced() Philippe Mathieu-Daudé
2021-05-25 13:46 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0 Philippe Mathieu-Daudé
2021-05-25 13:49 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1] Philippe Mathieu-Daudé
2021-05-25 13:50 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ??? Philippe Mathieu-Daudé
2021-05-25 14:00 ` Richard Henderson
2021-05-09 15:18 ` [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages Philippe Mathieu-Daudé
2021-05-25 7:55 ` [PATCH v2 " Philippe Mathieu-Daudé
2021-05-25 9:55 ` Peter Maydell
2021-05-25 10:18 ` Philippe Mathieu-Daudé
2021-05-25 14:32 ` Peter Maydell [this message]
2021-05-27 16:02 ` [PATCH " Philippe Mathieu-Daudé
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