Re: [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns

[Peter Maydell <peter.maydell@linaro.org>]

On 5 December 2013 12:39, Peter Maydell <peter.maydell@linaro.org> wrote:
> From: Alexander Graf <agraf@suse.de>
>
> Implement the B and BL instructions (PC relative branches and calls).
>
> For convenience in managing TCG temporaries which might be generated
> if a source register is the zero-register XZR, we provide a simple
> mechanism for creating a new temp which is automatically freed at the
> end of decode of the instruction.

> +static void init_tmp_a64_array(DisasContext *s)
> +{
> +    int i;
> +#ifdef CONFIG_DEBUG_TCG
> +    for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
> +        TCGV_UNUSED_I64(s->tmp_a64[i]);
> +    }
> +#endif
> +    s->tmp_a64_count = 0;
> +}

The "int i;" declaration needs to go inside the ifdef
to avoid a compilation failure when building with
debug disabled. Rather than resend this series all
over again, I propose to fix this nit as part of applying
the series to target-arm.next.

thanks
-- PMM