From: Peter Maydell <peter.maydell@linaro.org>
To: Jean-Philippe Brucker <jean-philippe@linaro.org>
Cc: richard.henderson@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 5/6] target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions
Date: Mon, 7 Aug 2023 10:54:05 +0100 [thread overview]
Message-ID: <CAFEAcA88J5QnuoJWOsVJj4qOhDHy-P4LMo+v5UdMLOQxy=pvQA@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-0p2UhURwgLRnUxSK8ktFsULsHz5x3pu+h80VOPBrZvQ@mail.gmail.com>
On Fri, 4 Aug 2023 at 19:08, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Wed, 2 Aug 2023 at 18:02, Jean-Philippe Brucker
> <jean-philippe@linaro.org> wrote:
> >
> > The AT instruction is UNDEFINED if the {NSE,NS} configuration is
> > invalid. Add a function to check this on all AT instructions that apply
> > to an EL lower than 3.
> >
> > Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > ---
> > target/arm/helper.c | 36 +++++++++++++++++++++++++-----------
> > 1 file changed, 25 insertions(+), 11 deletions(-)
> >
> > diff --git a/target/arm/helper.c b/target/arm/helper.c
> > index fbb03c364b..77dd80ad28 100644
> > --- a/target/arm/helper.c
> > +++ b/target/arm/helper.c
> > @@ -3616,6 +3616,20 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
> > #endif /* CONFIG_TCG */
> > }
> >
> > +static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri,
> > + bool isread)
> > +{
> > + /*
> > + * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
> > + * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved.
> > + */
> > + if (cpu_isar_feature(aa64_rme, env_archcpu(env)) &&
> > + (env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) {
> > + return CP_ACCESS_TRAP;
> > + }
>
> The AArch64.AT() pseudocode and the text in the individual
> AT insn descriptions ("When FEAT_RME is implemented, if the Effective
> value of SCR_EL3.{NSE, NS} is a reserved value, this instruction is
> UNDEFINED at EL3") say that this check needs an "arm_current_el(env) == 3"
> condition too.
It's been pointed out to me that since trying to return from
EL3 with SCR_EL3.{NSE,NS} == {1,0} is an illegal exception return,
it's not actually possible to try to execute these insns in this
state from any other EL than EL3. So we don't actually need
to check for EL3 here.
QEMU's implementation of exception return is missing that
check for illegal-exception-return on bad {NSE,NS}, though.
thanks
-- PMM
next prev parent reply other threads:[~2023-08-07 9:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-02 17:01 [PATCH v2 0/6] target/arm: Fixes for RME Jean-Philippe Brucker
2023-08-02 17:01 ` [PATCH v2 1/6] target/arm/ptw: Load stage-2 tables from realm physical space Jean-Philippe Brucker
2023-08-04 17:50 ` Peter Maydell
2023-08-02 17:01 ` [PATCH v2 2/6] target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2* Jean-Philippe Brucker
2023-08-04 17:55 ` Peter Maydell
2023-08-02 17:01 ` [PATCH v2 3/6] target/arm: Skip granule protection checks for AT instructions Jean-Philippe Brucker
2023-08-02 17:01 ` [PATCH v2 4/6] target/arm: Pass security space rather than flag " Jean-Philippe Brucker
2023-08-02 17:01 ` [PATCH v2 5/6] target/arm/helper: Check SCR_EL3.{NSE, NS} encoding " Jean-Philippe Brucker
2023-08-04 18:08 ` Peter Maydell
2023-08-07 9:54 ` Peter Maydell [this message]
2023-08-07 14:03 ` [PATCH v2 5/6] target/arm/helper: Check SCR_EL3.{NSE,NS} " Jean-Philippe Brucker
2023-08-07 15:08 ` [PATCH v2 5/6] target/arm/helper: Check SCR_EL3.{NSE, NS} " Peter Maydell
2023-08-02 17:01 ` [PATCH v2 6/6] target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK Jean-Philippe Brucker
2023-08-07 17:05 ` Peter Maydell
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