From: Peter Maydell <peter.maydell@linaro.org>
To: Stefano Stabellini <sstabellini@kernel.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>,
qemu-arm <qemu-arm@nongnu.org>,
julien.grall@arm.com
Subject: Re: [Qemu-devel] [PATCH v2] aarch64: advertise the GIC system register interface
Date: Tue, 7 Nov 2017 18:01:23 +0000 [thread overview]
Message-ID: <CAFEAcA8=Yrn53odaaSp+fvZ96sdLX4B5ZGZqf8FgYNjpCwYE+w@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1711070957150.30448@sstabellini-ThinkPad-X260>
On 7 November 2017 at 17:57, Stefano Stabellini <sstabellini@kernel.org> wrote:
> On Tue, 7 Nov 2017, Peter Maydell wrote:
>> I thought about this on the cycle into work this morning, and I
>> think that rather than require every board that uses gicv3
>> to set a property on the CPU, we should change the definition
>> of the id_aa64pfr0 register so that rather than being ARM_CP_CONST
>> it has a readfn, and then at runtime we can get that readfn to
>> add in the right bit if env->gicv3state is non-null.
>>
>> I'll put together a patch this afternoon.
>
> Great, please CC me when you do, I'll help you test the patch.
http://patchwork.ozlabs.org/patch/835300/ -- should already be
in your inbox somewhere...
thanks
-- PMM
prev parent reply other threads:[~2017-11-07 18:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-06 22:16 [Qemu-devel] [PATCH v2] aarch64: advertise the GIC system register interface Stefano Stabellini
2017-11-06 22:20 ` no-reply
2017-11-07 12:57 ` Peter Maydell
2017-11-07 17:57 ` Stefano Stabellini
2017-11-07 18:01 ` Peter Maydell [this message]
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