From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC8C7-0007ZG-7n for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:01:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC8C1-0000fk-JV for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:01:51 -0500 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]:54199) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eC8C1-0000dM-E8 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:01:45 -0500 Received: by mail-wr0-x22c.google.com with SMTP id u40so47015wrf.10 for ; Tue, 07 Nov 2017 10:01:45 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: From: Peter Maydell Date: Tue, 7 Nov 2017 18:01:23 +0000 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v2] aarch64: advertise the GIC system register interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefano Stabellini Cc: QEMU Developers , "xen-devel@lists.xen.org" , qemu-arm , julien.grall@arm.com On 7 November 2017 at 17:57, Stefano Stabellini wrote: > On Tue, 7 Nov 2017, Peter Maydell wrote: >> I thought about this on the cycle into work this morning, and I >> think that rather than require every board that uses gicv3 >> to set a property on the CPU, we should change the definition >> of the id_aa64pfr0 register so that rather than being ARM_CP_CONST >> it has a readfn, and then at runtime we can get that readfn to >> add in the right bit if env->gicv3state is non-null. >> >> I'll put together a patch this afternoon. > > Great, please CC me when you do, I'll help you test the patch. http://patchwork.ozlabs.org/patch/835300/ -- should already be in your inbox somewhere... thanks -- PMM