From: Peter Maydell <peter.maydell@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
Bin Meng <bin.meng@windriver.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Francisco Iglesias <francisco.iglesias@xilinx.com>,
qemu-arm <qemu-arm@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v7 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI
Date: Mon, 8 Mar 2021 17:15:43 +0000 [thread overview]
Message-ID: <CAFEAcA8BUZ_WFqY2RpcT-UX6f7Sa4fr2c9YG6Q3yTPem=ZRwfw@mail.gmail.com> (raw)
In-Reply-To: <20210303135254.3970-1-bmeng.cn@gmail.com>
On Wed, 3 Mar 2021 at 13:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
> is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
> crash. This is observed when testing VxWorks 7.
>
> We added a Xilinx CSU DMA model and the implementation is based on
> https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c
> and the one in Edgar's branch.
>
> The DST part of the model is verified along with ZynqMP GQSPI model.
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2021-03-08 17:34 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 13:52 [PATCH v7 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI Bin Meng
2021-03-03 13:52 ` [PATCH v7 1/5] hw/dma: Implement a Xilinx CSU DMA model Bin Meng
2021-03-10 13:59 ` Peter Maydell
2021-03-03 13:52 ` [PATCH v7 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Bin Meng
2021-03-03 13:52 ` [PATCH v7 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI Bin Meng
2021-03-03 13:52 ` [PATCH v7 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Bin Meng
2021-03-03 13:52 ` [PATCH v7 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips Bin Meng
2021-03-08 17:15 ` Peter Maydell [this message]
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