From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0scP-0000wc-NB for qemu-devel@nongnu.org; Thu, 12 May 2016 11:33:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b0scO-0002W5-Gj for qemu-devel@nongnu.org; Thu, 12 May 2016 11:33:41 -0400 Received: from mail-vk0-x234.google.com ([2607:f8b0:400c:c05::234]:32977) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0scO-0002Vz-76 for qemu-devel@nongnu.org; Thu, 12 May 2016 11:33:40 -0400 Received: by mail-vk0-x234.google.com with SMTP id o133so102371995vka.0 for ; Thu, 12 May 2016 08:33:40 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1463059985-2272-1-git-send-email-peter.maydell@linaro.org> References: <1463059985-2272-1-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Thu, 12 May 2016 16:33:20 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PULL 00/43] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers On 12 May 2016 at 14:32, Peter Maydell wrote: > Big fat pullreq of accumulated ARM patches. There are some more > things on my to-review queue still but this is plenty for > one pull request... > > > The following changes since commit 26617924e9a329bdff81936d2d277983f0c4d372: > > Open 2.7 development tree (2016-05-12 12:35:25 +0100) > > are available in the git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160512 > > for you to fetch changes up to 0bc91ab3bb70f836d5a7a3ef6f800ef8c22e936f: > > hw/arm: QOM'ify versatilepb.c (2016-05-12 13:42:12 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * blizzard, omap_lcdc: code cleanup to remove DEPTH != 32 dead code > * QOMify various ARM devices > * bcm2835_property: use cached values when querying framebuffer > * hw/arm/nseries: don't allocate large sized array on the stack > * fix LPAE descriptor address masking (only visible for EL2) > * fix stage 2 exec permission handling for AArch32 > * first part of supporting syndrome info for data aborts to EL2 > * virt: NUMA support > * work towards i.MX6 support > * avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes > Applied, thanks. -- PMM