From: Peter Maydell <peter.maydell@linaro.org>
To: Rebecca Cran <rebecca@nuviainc.com>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 0/3] target/arm: Add support for FEAT_SSBS
Date: Fri, 5 Mar 2021 11:22:24 +0000 [thread overview]
Message-ID: <CAFEAcA8CfHe6NaaSF5S2cz=SkKOQoSOjsdMVqDUbM0D7R_EXfw@mail.gmail.com> (raw)
In-Reply-To: <20210216224543.16142-1-rebecca@nuviainc.com>
On Tue, 16 Feb 2021 at 22:45, Rebecca Cran <rebecca@nuviainc.com> wrote:
>
>
> Add support for FEAT_SSBS, Speculative Store Bypass Safe. SSBS is an
> optional feature in ARMv8.0 and is mandatory in ARMv8.5.
>
> Changes from v1 to v2:
>
> o Removed changes to cpsr_write_from_spsr_elx and cpsr_read_for_spsr_elx.
> o Moved the SSBS case in translate-a64.c above DIT to keep the numbers in
> order.
> o Moved the check for SCTLR_DSSBS_32 in take_aarch32_exception.
>
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2021-03-05 11:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-16 22:45 [PATCH v2 0/3] target/arm: Add support for FEAT_SSBS Rebecca Cran
2021-02-16 22:45 ` [PATCH v2 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe Rebecca Cran
2021-02-17 3:45 ` Richard Henderson
2021-03-01 14:42 ` Rebecca Cran
2021-02-16 22:45 ` [PATCH v2 2/3] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Rebecca Cran
2021-02-16 22:45 ` [PATCH v2 3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Rebecca Cran
2021-03-05 11:31 ` Peter Maydell
2021-03-05 15:23 ` Rebecca Cran
2021-03-05 11:22 ` Peter Maydell [this message]
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