From: Peter Maydell <peter.maydell@linaro.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jamin Lin" <jamin_lin@aspeedtech.com>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>, "Bin Meng" <bmeng.cn@gmail.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:SD (Secure Card)" <qemu-block@nongnu.org>,
troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com
Subject: Re: [PATCH v3 0/3] Introduce a new Write Protected pin inverted property
Date: Tue, 7 Jan 2025 22:36:39 +0000 [thread overview]
Message-ID: <CAFEAcA8Dz6b0fVjhEntNbbbb4UpBikUXsOmzU4WNabbrac+6Sg@mail.gmail.com> (raw)
In-Reply-To: <53d67dbf-b595-4442-81e7-84267aa8e511@kaod.org>
On Tue, 7 Jan 2025 at 17:55, Cédric Le Goater <clg@kaod.org> wrote:
>
> Hello,
>
> > I would not recommend using qemu_irq_invert() in new code.
> >
> > I guess in an ideal world we'd implement a QOM object
> > that encapsulated the the "not gate" logic, similar to
> > TYPE_OR_IRQ. (Though for TYPE_OR_IRQ we made the mistake
> > of making it inherit from TYPE_DEVICE, not TYPE_SYSBUS_DEVICE,
> > so it doesn't get reset properly on system reset and so
> > the "what happens to the output on reset" is still not
> > really correct.)
>
> I see how this would work with TYPE_PL181 model but I don't
> understand how this could work with TYPE_SYSBUS_SDHCI since
> we don't have a gpio line to invert the level. Am I missing
> something ?
You have a gpio line, i.e. a qemu_irq, because you're passing
it to qemu_irq_invert(), and you could instead connect it into
a hypothetical TYPE_NOT_IRQ device. qemu_irq are GPIO lines,
the type just has an odd name for historical reasons.
-- PMM
next prev parent reply other threads:[~2025-01-07 22:37 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 9:48 [PATCH v3 0/3] Introduce a new Write Protected pin inverted property Jamin Lin via
2024-11-14 9:48 ` [PATCH v3 1/3] hw/sd/sdhci: Fix coding style Jamin Lin via
2025-01-07 19:28 ` Philippe Mathieu-Daudé
2024-11-14 9:48 ` [PATCH v3 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Jamin Lin via
2025-01-07 19:29 ` Philippe Mathieu-Daudé
2025-01-21 10:38 ` Cédric Le Goater
2025-01-22 2:04 ` Jamin Lin
2024-11-14 9:48 ` [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB Jamin Lin via
2025-01-07 19:29 ` Philippe Mathieu-Daudé
2024-11-27 9:44 ` [PATCH v3 0/3] Introduce a new Write Protected pin inverted property Cédric Le Goater
2024-11-27 11:23 ` Philippe Mathieu-Daudé
2024-11-27 11:26 ` Cédric Le Goater
2024-11-28 11:06 ` Peter Maydell
2025-01-07 17:54 ` Cédric Le Goater
2025-01-07 22:36 ` Peter Maydell [this message]
2025-01-08 9:11 ` Cédric Le Goater
2024-11-28 5:37 ` Jamin Lin
2025-01-07 18:16 ` Cédric Le Goater
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