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Tue, 07 Jan 2025 14:36:50 -0800 (PST) MIME-Version: 1.0 References: <20241114094839.4128404-1-jamin_lin@aspeedtech.com> <2e956389-289a-4806-8985-ab846d808736@kaod.org> <53d67dbf-b595-4442-81e7-84267aa8e511@kaod.org> In-Reply-To: <53d67dbf-b595-4442-81e7-84267aa8e511@kaod.org> From: Peter Maydell Date: Tue, 7 Jan 2025 22:36:39 +0000 X-Gm-Features: AbW1kvao-OSrFjrvLlCeougddZRu-3ILtDjF3HoNrbR0Ri3vuvdD7Ywk5sY2Qgc Message-ID: Subject: Re: [PATCH v3 0/3] Introduce a new Write Protected pin inverted property To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jamin Lin , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" , troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=peter.maydell@linaro.org; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 7 Jan 2025 at 17:55, C=C3=A9dric Le Goater wrote: > > Hello, > > > I would not recommend using qemu_irq_invert() in new code. > > > > I guess in an ideal world we'd implement a QOM object > > that encapsulated the the "not gate" logic, similar to > > TYPE_OR_IRQ. (Though for TYPE_OR_IRQ we made the mistake > > of making it inherit from TYPE_DEVICE, not TYPE_SYSBUS_DEVICE, > > so it doesn't get reset properly on system reset and so > > the "what happens to the output on reset" is still not > > really correct.) > > I see how this would work with TYPE_PL181 model but I don't > understand how this could work with TYPE_SYSBUS_SDHCI since > we don't have a gpio line to invert the level. Am I missing > something ? You have a gpio line, i.e. a qemu_irq, because you're passing it to qemu_irq_invert(), and you could instead connect it into a hypothetical TYPE_NOT_IRQ device. qemu_irq are GPIO lines, the type just has an odd name for historical reasons. -- PMM