From: Peter Maydell <peter.maydell@linaro.org>
To: Mihai Carabas <mihai.carabas@oracle.com>
Cc: Peng Hao <peng.hao2@zte.com.cn>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 5/6] pvpanic : update pvpanic document
Date: Mon, 14 Dec 2020 10:30:18 +0000 [thread overview]
Message-ID: <CAFEAcA8EE6Vz_VikBg5dyFru-fKomSd4rcUopkM7tF=Heh01Vw@mail.gmail.com> (raw)
In-Reply-To: <1603891979-11961-6-git-send-email-mihai.carabas@oracle.com>
On Wed, 28 Oct 2020 at 14:26, Mihai Carabas <mihai.carabas@oracle.com> wrote:
>
> From: Peng Hao <peng.hao2@zte.com.cn>
>
> Add mmio mode as a pci device support info in docs/specs/pvpanic.txt.
>
> Signed-off-by: Peng Hao <peng.hao2@zte.com.cn>
> Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
> ---
> docs/specs/pvpanic.txt | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
> index a90fbca..4258922 100644
> --- a/docs/specs/pvpanic.txt
> +++ b/docs/specs/pvpanic.txt
> @@ -1,7 +1,7 @@
> PVPANIC DEVICE
> ==============
>
> -pvpanic device is a simulated ISA device, through which a guest panic
> +pvpanic device is a simulated device, through which a guest panic
> event is sent to qemu, and a QMP event is generated. This allows
> management apps (e.g. libvirt) to be notified and respond to the event.
>
> @@ -9,6 +9,9 @@ The management app has the option of waiting for GUEST_PANICKED events,
> and/or polling for guest-panicked RunState, to learn when the pvpanic
> device has fired a panic event.
>
> +The pvpanic device can be implemented as an ISA device (using IOPORT),
> +or, since qemu 4.0, as a PCI device.
Version number is outdated here. I would simply say "or as a PCI device".
> +
> ISA Interface
> -------------
>
> @@ -24,6 +27,13 @@ bit 1: a guest panic has happened and will be handled by the guest;
> the host should record it or report it, but should not affect
> the execution of the guest.
>
> +PCI Interface
> +-------------
> +
> +The PCI interface is similar to the ISA interface except that it uses an MMIO
> +address space provided by its BAR0.
You should be specific about the access width(s) permitted here --
is the access to the register 8-bit only, 32-bit-only, or what ?
> For example, the arm virt machine may
> +enable a pvpanic device by adding '-device pvpanic-pci' to the command line.
No need to be specific to Arm virt here.
"Any machine with a PCI device can enable a pvpanic device by adding
'-device pvpanic-pci' to the command line."
> +
> ACPI Interface
> --------------
thanks
-- PMM
next prev parent reply other threads:[~2020-12-14 10:32 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 13:32 [PATCH] Add support for pvpanic pci device Mihai Carabas
2020-10-28 13:32 ` [PATCH 1/6] hw/misc/pvpanic: Build the pvpanic device for any machine Mihai Carabas
2020-12-14 10:47 ` Peter Maydell
2020-12-14 10:54 ` Peter Maydell
2020-10-28 13:32 ` [PATCH 2/6] hw/misc/pvpanic: Cosmetic renaming Mihai Carabas
2020-12-14 10:20 ` Peter Maydell
2020-10-28 13:32 ` [PATCH 3/6] hw/misc/pvpanic: Add the PCI interface Mihai Carabas
2020-12-14 10:58 ` Peter Maydell
2020-10-28 13:32 ` [PATCH 4/6] hw/arm/virt: Use the pvpanic pci device Mihai Carabas
2020-12-14 10:24 ` Peter Maydell
2020-10-28 13:32 ` [PATCH 5/6] pvpanic : update pvpanic document Mihai Carabas
2020-12-14 10:30 ` Peter Maydell [this message]
2020-10-28 13:32 ` [PATCH 6/6] pvpanic: break dependency on ISA_BUS adding PCI Mihai Carabas
2020-10-29 12:30 ` [PATCH] Add support for pvpanic pci device Mihai Carabas
2020-11-23 13:42 ` Mihai Carabas
2020-12-14 11:03 ` Peter Maydell
2020-12-14 11:15 ` Mihai Carabas
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