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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 1/4] target/arm: Add TB flag for "MVE insns not predicated"
Date: Fri, 3 Sep 2021 15:17:45 +0100	[thread overview]
Message-ID: <CAFEAcA8EoyaCSzA1vL_SHY50T6Fxjm420_pYgXx1_+E-nV-MBA@mail.gmail.com> (raw)
In-Reply-To: <76cd3594-f864-232c-8687-19a1d44ff07e@linaro.org>

On Fri, 3 Sept 2021 at 14:58, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/2/21 5:09 PM, Peter Maydell wrote:
> > Our current codegen for MVE always calls out to helper functions,
> > because some byte lanes might be predicated. The common case is
> > that in fact there is no predication active and all lanes should
> > be updated together, so we can produce better code by detecting
> > that and using the TCG generic vector infrastructure.
> >
> > Add a TB flag that is set when we can guarantee that there
> > is no active MVE predication, and a bool in the DisasContext.
> > Subsequent patches will use this flag to generate improved
> > code for some instructions.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > Another of those awkward-to-review patches where the interesting
> > question is "did I miss anywhere where we set v7m.vpr to non-0
> > or v7m.ltpsize to non-4 while in the middle of a TB ?" ...
> >
> > I've left the TB flag as non-cached because there seemed to
> > be an irritatingly large set of places where we'd have to do
> > an hflags recomputation.
>
> Indeed, non-cached seems like the right option.
>
> > +static bool mve_no_predication(CPUARMState *env)
> > +{
> > +    /*
> > +     * Return true if there is definitely no predication of MVE
> > +     * instructions for any reason. (Returning false even if there
> > +     * isn't any predication is OK; generated code will just be
> > +     * a little worse.)
> > +     * We do not account here for partial insn execution due to
> > +     * ECI bits as those are already in the TB flags elsewhere.
> > +     */
>
> I think you should go ahead and include that here, as it makes the test self-contained,
> and avoids you having to do this:
>
> > +        dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED) && dc->eci == 0;

Yeah. I think I was initially thinking that I wanted the MVE_NO_PRED
flag to be cached in hflags, in which case you have to do the combination
with ECI here because the ECI/condexec bits are not cached. But if we're
happy for MVE_NO_PRED to be not cached then we can happily combine with
ECI directly in mve_no_predication().

> > +    /* VLLDM or VLSTM helpers might have updated vpr or ltpsize */
> > +    s->mve_no_pred = false;
>
> For a moment I was thinking that this was ok, just finish the rest of the TB and resync
> naturally, letting the end of the TB use the helpers.  But then I thought about goto_tb.
> If you have this potentially variable condition, you can't chain the links between this TB
> and the next.

I don't really understand what you mean here. What's the difference
between ending the TB now and translating a few more insns in
this TB before we end it?

thanks
-- PMM


  reply	other threads:[~2021-09-03 14:20 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 15:09 [PATCH 0/4] target/arm: Use TCG vector ops for MVE Peter Maydell
2021-09-02 15:09 ` [PATCH 1/4] target/arm: Add TB flag for "MVE insns not predicated" Peter Maydell
2021-09-03 13:57   ` Richard Henderson
2021-09-03 14:17     ` Peter Maydell [this message]
2021-09-03 15:28       ` Richard Henderson
2021-09-03 16:30         ` Peter Maydell
2021-09-07 14:11           ` Richard Henderson
2021-09-07 14:22             ` Richard Henderson
2021-09-10 16:00             ` Peter Maydell
2021-09-12 12:48               ` Richard Henderson
2021-09-09 13:46     ` Peter Maydell
2021-09-10  6:46       ` Richard Henderson
2021-09-10  9:30         ` Peter Maydell
2021-09-10 13:08           ` Richard Henderson
2021-09-09 14:53     ` Peter Maydell
2021-09-02 15:09 ` [PATCH 2/4] target/arm: Optimize MVE logic ops Peter Maydell
2021-09-02 16:19   ` Philippe Mathieu-Daudé
2021-09-03 13:58   ` Richard Henderson
2021-09-02 15:09 ` [PATCH 3/4] target/arm: Optimize MVE arithmetic ops Peter Maydell
2021-09-02 16:20   ` Philippe Mathieu-Daudé
2021-09-03 13:59   ` Richard Henderson
2021-09-02 15:09 ` [PATCH 4/4] target/arm: Optimize MVE VNEG, VABS Peter Maydell
2021-09-02 16:21   ` Philippe Mathieu-Daudé
2021-09-03 14:00   ` Richard Henderson
2021-09-03 15:14 ` [PATCH 0/4] target/arm: Use TCG vector ops for MVE Richard Henderson
2021-09-03 15:20   ` Peter Maydell
2021-09-03 15:36     ` Richard Henderson

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