From: Peter Maydell <peter.maydell@linaro.org>
To: Salil Mehta <salil.mehta@huawei.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
Salil Mehta <salil.mehta@opnsrc.net>,
Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH] hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 from kernel in cpuif reset
Date: Tue, 14 Oct 2025 16:23:40 +0100 [thread overview]
Message-ID: <CAFEAcA8GsSDnY8GEJZYNbJ3KZAp9tJ=s_vUBB_XwwGaEwozxzQ@mail.gmail.com> (raw)
In-Reply-To: <a630fc58d9f946988bd6c27479543dd1@huawei.com>
On Tue, 14 Oct 2025 at 16:13, Salil Mehta <salil.mehta@huawei.com> wrote:
>
> > From: Peter Maydell <peter.maydell@linaro.org>
> > In what situation do we ever start running a VCPU before the *GIC* has
> > been realized? The GIC should get realized as part of creating the virt board,
> > which must complete before we do anything like running a vcpu.
>
>
> Just after realization of vCPU in the machvirt_init() you can see the default
> power_state is PSCI CPU_ON, which means KVM_MP_STATE_RUNNABLE.
> Since, the thread is up and not doing IO wait in userspace it gets into
> cpu_exec() loop and actually run KVM_RUN IOCTL. Inside the KVM it
> momentarily takes the vCPU mutex but later exit and releases. This keeps
> going on for all of the vCPU threads realized early.
Yikes. We definitely should fix that : letting the vcpu run
before we get to qemu_machine_creation_done() seems like it
would be a massive source of race conditions.
-- PMM
next prev parent reply other threads:[~2025-10-14 15:24 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-14 10:24 [PATCH] hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 from kernel in cpuif reset Peter Maydell
2025-10-14 10:41 ` Salil Mehta via
2025-10-14 13:23 ` Salil Mehta via
2025-10-14 13:31 ` Peter Maydell
2025-10-14 13:41 ` Salil Mehta via
2025-10-14 13:49 ` Peter Maydell
2025-10-14 14:22 ` Salil Mehta via
2025-10-14 14:28 ` Peter Maydell
2025-10-14 14:48 ` Salil Mehta via
2025-10-14 14:59 ` Peter Maydell
2025-10-14 15:13 ` Salil Mehta via
2025-10-14 15:16 ` Salil Mehta via
2025-10-14 15:23 ` Peter Maydell [this message]
2025-10-14 15:32 ` Salil Mehta via
2025-10-14 15:43 ` Peter Maydell
2025-10-14 15:54 ` Salil Mehta via
2025-10-14 19:36 ` Salil Mehta via
2025-10-17 1:43 ` Salil Mehta
2025-10-14 16:07 ` Salil Mehta via
2025-10-14 16:12 ` Peter Maydell
2025-10-14 15:39 ` Salil Mehta via
2025-10-16 12:09 ` Salil Mehta via
2025-10-15 10:58 ` Salil Mehta via
2025-10-15 12:06 ` Peter Maydell
2025-10-16 11:13 ` Salil Mehta via
2025-10-16 12:46 ` Peter Maydell
2025-10-16 15:28 ` Salil Mehta
2025-10-16 15:46 ` Peter Maydell
2025-10-16 15:48 ` Salil Mehta via
2025-10-16 12:17 ` Salil Mehta via
2025-10-16 12:22 ` Peter Maydell
2025-10-16 12:36 ` Salil Mehta
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