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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Alexander Graf <agraf@suse.de>,
	C Fontana <claudio.fontana@linaro.org>,
	Dirk Mueller <dmueller@suse.de>,
	Laurent Desnogues <laurent.desnogues@gmail.com>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
Subject: Re: [Qemu-devel] [PATCH 12/12] target-arm: A64: add support for compare and branch imm
Date: Wed, 4 Dec 2013 17:02:36 +0000	[thread overview]
Message-ID: <CAFEAcA8H26saczutidFwM7YE-anBzu3jqsk+HUkhv4zLqX2FYg@mail.gmail.com> (raw)
In-Reply-To: <529E7BC8.6070100@twiddle.net>

On 4 December 2013 00:48, Richard Henderson <rth@twiddle.net> wrote:
> On 12/04/2013 01:32 PM, Peter Maydell wrote:
>> You're right that we can just make this function return the TCGv
>> temp rather than making the caller pass one in. Are you suggesting
>> the 64-bit case should return cpu_X[reg] rather than a copy of it,
>> though? I think it would be pretty hard to reason about if you had to
>> remember that sometimes you got a trashable copy and sometimes
>> the real register.
>
> I think that the normal case is to write to the output in one step, and thus
> having an input overlap an output isn't your problem but tcg's.  I would think
> the case of multi-step output to be fairly rare, and easily solvable by always
> allocating an output temporary.

So I had a look at this, and it seems to make code like this (from
the handling for logic ops with shifted registers):

    tcg_rm = read_cpu_reg(s, rm, sf);

    if (shift_amount) {
        shift_reg_imm(tcg_rm, tcg_rm, sf,
                      shift_type, shift_amount);
    }

    if (invert) {
        tcg_gen_not_i64(tcg_rm, tcg_rm);
        /* we zero extend later on (!sf) */
    }

a bit awkward if the value returned from read_cpu_reg() isn't a
trashable copy, because of the sequence of "maybe we need
to change the value like this" conditionals. The code basically
needs to copy the return value from read_cpu_reg() into its
own temporary immediately. There's a similar thing in the
conditional-select code where the else-case's value might be
inverted and might be incremented and might be neither.

I think that kind of thing tips the balance in favour of having
read_cpu_reg() always return a trashable temporary.

thanks
-- PMM

  parent reply	other threads:[~2013-12-04 17:03 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-03 21:51 [Qemu-devel] [PATCH 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 01/12] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() Peter Maydell
2013-12-03 23:34   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 02/12] target-arm: A64: add set_pc cpu method Peter Maydell
2013-12-03 23:35   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR Peter Maydell
2013-12-03 23:39   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 04/12] target-arm: Support fp registers in gdb stub Peter Maydell
2013-12-03 23:40   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 05/12] target-arm: A64: add stubs for a64 specific helpers Peter Maydell
2013-12-03 23:41   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 06/12] target-arm: A64: provide skeleton for a64 insn decoding Peter Maydell
2013-12-03 23:41   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 07/12] target-arm: A64: expand decoding skeleton for system instructions Peter Maydell
2013-12-03 23:15   ` Christopher Covington
2013-12-04  0:21     ` Peter Maydell
2013-12-03 23:49   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 08/12] target-arm: A64: add support for B and BL insns Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 09/12] target-arm: A64: add support for BR, BLR and RET insns Peter Maydell
2013-12-04  0:00   ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 10/12] target-arm: A64: add support for conditional branches Peter Maydell
2013-12-04  0:03   ` Richard Henderson
2013-12-04  0:22     ` Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 11/12] target-arm: A64: add support for 'test and branch' imm Peter Maydell
2013-12-04  0:07   ` Richard Henderson
2013-12-04  0:22     ` Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 12/12] target-arm: A64: add support for compare and branch imm Peter Maydell
2013-12-04  0:10   ` Richard Henderson
2013-12-04  0:32     ` Peter Maydell
2013-12-04  0:48       ` Richard Henderson
2013-12-04 11:05         ` Peter Maydell
2013-12-04 17:02         ` Peter Maydell [this message]
2013-12-04 17:31           ` Richard Henderson

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