From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fNgSl-0000a1-Ib for qemu-devel@nongnu.org; Tue, 29 May 2018 11:23:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fNgSk-00069J-Gu for qemu-devel@nongnu.org; Tue, 29 May 2018 11:23:03 -0400 Received: from mail-ot0-x241.google.com ([2607:f8b0:4003:c0f::241]:42326) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fNgSk-000695-Av for qemu-devel@nongnu.org; Tue, 29 May 2018 11:23:02 -0400 Received: by mail-ot0-x241.google.com with SMTP id l13-v6so17394657otk.9 for ; Tue, 29 May 2018 08:23:02 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20180529041946.9481-1-joel@jms.id.au> References: <20180529041946.9481-1-joel@jms.id.au> From: Peter Maydell Date: Tue, 29 May 2018 16:22:41 +0100 Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v3] aspeed_scu: Implement RNG register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Joel Stanley Cc: QEMU Developers , qemu-arm , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= On 29 May 2018 at 05:19, Joel Stanley wrote: > The ASPEED SoCs contain a single register that returns random data when > read. This models that register so that guests can use it. > > The random number data register has a corresponding control register, > however it returns data regardless of the state of the enabled bit, so > the model follows this behaviour. > > Reviewed-by: C=C3=A9dric Le Goater > Signed-off-by: Joel Stanley > --- > v2: > - Remove call to qcrypto_random_init as this is done in main() > v3: > - Add C=C3=A9dric's reviewed-by > - Add a comment about why we don't check for the rng enable bit > --- > hw/misc/aspeed_scu.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index 5e6d5744eeca..96db052389cc 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -16,6 +16,7 @@ > #include "qapi/visitor.h" > #include "qemu/bitops.h" > #include "qemu/log.h" > +#include "crypto/random.h" > #include "trace.h" > > #define TO_REG(offset) ((offset) >> 2) > @@ -154,6 +155,18 @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_N= R_REGS] =3D { > [BMC_DEV_ID] =3D 0x00002402U > }; > > +static uint32_t aspeed_scu_get_random(void) > +{ > + Error *err =3D NULL; > + uint32_t num; > + > + if (qcrypto_random_bytes((uint8_t *)&num, sizeof(num), &err)) { > + error_report_err(err); > + } > + > + return num; > +} This will return an uninitialized value if qcrypto_random_bytes() fails. Does the guest use this value for cryptographic purposes? In hw/misc/bcm2835_rng.c we opted to make qcrypto_random_bytes() failing be fatal (for reasons noted in the comment there), though that is a bit rough. exynos4210_rng() is more conveniently able to just never report to the guest that the PRNG is ready. thanks -- PMM