Re: Resources on deeper understanding of Translation blocks

[Peter Maydell <peter.maydell@linaro.org>]

On Tue, 16 May 2023 at 16:27, Alex Bennée <alex.bennee@linaro.org> wrote:
> Gautam Bhat <mindentropy@gmail.com> writes:
> > 3. Do you have more information or a visual diagram of sorts for
> > TARGET_PAGE_* and PAGE_* and the relation between translation blocks
> > and pages? Also how
> > should one handle where architectures don't have any paging?
>
> All system emulation is handled by page size because that is the
> fundamental granularity of the softmmu TLB which looks up a translation
> from guest address to offset into the memory region. It is not directly
> related to if the guest is using paging to implement virtual memory.

Also, each target defines a TARGET_PAGE_BITS even if the
target architecture doesn't have the concept of paging.
This specifies the minimum granularity at which you can
change things like r/w protection on addresses, so if your
target architecture has an MPU that might affect what
you want to set it to. If yo uhave neither an MPU nor an MMU,
you could look at what granularity/spacing typical systems
have between devices and particularly between devices and RAM.
If you have no pressing reason to set it to something as
a result of thinking about all that, then 4K pages is
probably as good a value as any.

-- PMM