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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jean-Philippe Brucker , "Michael S. Tsirkin" , Robin Murphy , zhangfei.gao@foxmail.com, QEMU Developers , Peter Xu , qemu-arm , Shameerali Kolothum Thodi , Will Deacon , Rob Herring , Eric Auger Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 8 Jul 2020 at 15:20, Eric Auger wrote: > > Add the support for AIDR register. It currently advertises > SMMU V3.0 spec. > > Signed-off-by: Eric Auger > > --- > --- > hw/arm/smmuv3-internal.h | 1 + > include/hw/arm/smmuv3.h | 1 + > hw/arm/smmuv3.c | 3 +++ > 3 files changed, 5 insertions(+) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index ef093eaff5..6296235020 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -64,6 +64,7 @@ REG32(IDR5, 0x14) > #define SMMU_IDR5_OAS 4 > > REG32(IIDR, 0x18) > +REG32(AIDR, 0x1C) Rest of file uses lowercase letters for hex values, so "0x1c". > REG32(CR0, 0x20) > FIELD(CR0, SMMU_ENABLE, 0, 1) > FIELD(CR0, EVENTQEN, 2, 1) Otherwise Reviewed-by: Peter Maydell thanks -- PMM