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X-Received-From: 2607:f8b0:4864:20::341 Subject: Re: [Qemu-devel] [PATCH for-4.1] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christophe Lyon , qemu-arm , Richard Henderson , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 11 Jul 2019 at 14:01, Alex Benn=C3=A9e wro= te: > > > Peter Maydell writes: > > > The ARMv5 architecture didn't specify detailed per-feature ID > > registers. Now that we're using the MVFR0 register fields to > > gate the existence of VFP instructions, we need to set up > > the correct values in the cpu->isar structure so that we still > > provide an FPU to the guest. > > > > This fixes a regression in the arm926 and arm1026 CPUs, which > > are the only ones that both have VFP and are ARMv5 or earlier. > > This regression was introduced by the VFP refactoring, and more > > specifically by commits 1120827fa182f0e76 and 266bd25c485597c, > > which accidentally disabled VFP short-vector support and > > double-precision support on these CPUs. > > > > Reported-by: Christophe Lyon > > Signed-off-by: Peter Maydell > > Fixes: 1120827fa182f0e > > Fixes: 266bd25c485597c > > Fixes: https://bugs.launchpad.net/qemu/+bug/1836192 > > --- > > I've followed the existing approach we used for ISAR1 here > > of just filling in the fields we care about, rather than trying > > to set the entire register value. > > Reviewed-by: Alex Benn=C3=A9e > > Do you think we have caught them all now? If we end up removing the > other ARM_FEATURE_foo flags in favour of isar tests we shall have to be > careful not to re-introduce these sort of bugs. I checked that these were the only two extra ID-reg checks we added as part of the VFP conversion, at any rate (ignoring the checks for features the ARMv5 cores don't have). thanks -- PMM