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From: Peter Maydell <peter.maydell@linaro.org>
Date: Mon, 9 Nov 2015 11:22:36 +0000
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Subject: Re: [Qemu-devel] [PATCH 09/16] target-arm: Support multiple address
 spaces in page table walks
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To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Patch Tracking <patches@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, qemu-arm@nongnu.org, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, =?UTF-8?Q?Andreas_F=C3=A4rber?= <afaerber@suse.de>

On 9 November 2015 at 11:19, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
>
> On 09/11/2015 12:09, Peter Maydell wrote:
>>>> >> I could have handled that by making the CPU init code always
>>>> >> register two ASes (using the same one twice if the board code
>>>> >> only passes one or using system_address_space twice if the
>>>> >> board code doesn't pass one at all), but that seemed a bit wasteful.
>>> >
>>> > I think it's simpler though.  Complicating the init code is better than
>>> > handling the condition throughout all the helpers...
>> It was the overhead of having an extra AddressSpace that concerned
>> me (plus it shows up in things like 'info mtree' somewhat confusingly
>> if you didn't expect your board to really have 2 ASes).
>
> I don't think it shows up twice with address_space_init_shareable, does it?

Yes, looking at the code you're right.

-- PMM