Re: [Qemu-devel] [PATCH v3 07/15] target-arm: Add TTBR0_EL2

[Peter Maydell <peter.maydell@linaro.org>]

On 29 May 2015 at 07:43, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target-arm/helper.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index df07a6a..193750b 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2533,6 +2533,12 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
>      { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "HTTBR", .cp = 15, .crm = 2, .opc1 = 4,

Preferred order: opc1, crm. Will fixup.

> +    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
> +      .access = PL2_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
> +    { .name = "HTTBR", .cp = 15, .crm = 2, .opc1 = 4,
> +      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
> +      .writefn = vmsa_ttbr_write, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },

There's no ASID in a TTBR0_EL2/HTTBR, so we don't need to
use the vmsa_ttbr_write function. Will drop that field
setting.

-- PMM