From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RlOob-0002MO-H8 for qemu-devel@nongnu.org; Thu, 12 Jan 2012 12:51:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RlOoV-0006ae-Mi for qemu-devel@nongnu.org; Thu, 12 Jan 2012 12:51:53 -0500 Received: from mail-pw0-f45.google.com ([209.85.160.45]:44035) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RlOoV-0006aV-I5 for qemu-devel@nongnu.org; Thu, 12 Jan 2012 12:51:47 -0500 Received: by pbdd7 with SMTP id d7so631239pbd.4 for ; Thu, 12 Jan 2012 09:51:46 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1326299490-10780-6-git-send-email-mark.langsdorf@calxeda.com> References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com> <1326299490-10780-1-git-send-email-mark.langsdorf@calxeda.com> <1326299490-10780-6-git-send-email-mark.langsdorf@calxeda.com> Date: Thu, 12 Jan 2012 17:51:46 +0000 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Langsdorf Cc: i.mitsyanko@gmail.com, edgar.iglesias@gmail.com, qemu-devel@nongnu.org, Rob Herring , afaerber@suse.de On 11 January 2012 16:31, Mark Langsdorf wrote= : > + =C2=A0 =C2=A0highbank_binfo.ram_size =3D ram_size; > + =C2=A0 =C2=A0highbank_binfo.kernel_filename =3D kernel_filename; > + =C2=A0 =C2=A0highbank_binfo.kernel_cmdline =3D kernel_cmdline; > + =C2=A0 =C2=A0highbank_binfo.initrd_filename =3D initrd_filename; > + =C2=A0 =C2=A0highbank_binfo.board_id =3D -1; /* provided by deviceTree = */ > + =C2=A0 =C2=A0highbank_binfo.nb_cpus =3D smp_cpus; > + =C2=A0 =C2=A0highbank_binfo.loader_start =3D 0; > + =C2=A0 =C2=A0highbank_binfo.smp_loader_start =3D SMP_BOOT_ADDR; > + =C2=A0 =C2=A0arm_load_kernel(env, &highbank_binfo); So at the moment this will use address 0x10000030 as the location that the bootloader for secondary CPUs polls to find out whether it can release the secondary CPUs. This is right for realview and vexpress, because it's the sysreg SYS_FLAGS (implemented in arm_sysctl.c). Is this really the right location to poll for Highbank? (There's a patch in the Samsung Exynos4 patch series which addresses this by allowing boards to specify a polling location. So I'm wondering what that location ought to be for Highbank...) thanks -- PMM