From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:50274)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1Y769G-0008KO-9U
	for qemu-devel@nongnu.org; Fri, 02 Jan 2015 12:36:31 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1Y769D-00047Z-3k
	for qemu-devel@nongnu.org; Fri, 02 Jan 2015 12:36:30 -0500
Received: from mail-la0-f49.google.com ([209.85.215.49]:60789)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1Y769C-00047U-SZ
	for qemu-devel@nongnu.org; Fri, 02 Jan 2015 12:36:27 -0500
Received: by mail-la0-f49.google.com with SMTP id hs14so15464611lab.22
	for <qemu-devel@nongnu.org>; Fri, 02 Jan 2015 09:36:26 -0800 (PST)
MIME-Version: 1.0
In-Reply-To: <54A6B6A3.9070208@redhat.com>
References: <1420208303-24111-1-git-send-email-ard.biesheuvel@linaro.org>
	<54A6B6A3.9070208@redhat.com>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 2 Jan 2015 17:36:05 +0000
Message-ID: <CAFEAcA8OdONLG9m_n7jTorPLYp8hGVRx1+=S-oQwNhUsB2_Y-Q@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH] target-arm: crypto: fix BE host support
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Laszlo Ersek <lersek@redhat.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Ard Biesheuvel <ard.biesheuvel@linaro.org>

On 2 January 2015 at 15:17, Laszlo Ersek <lersek@redhat.com> wrote:
> On 01/02/15 15:18, Ard Biesheuvel wrote:
>> (ie if you store 0x112233445566778899aabbccddeeff00 as a 64 bit write
>> to VFP register D0 then regs[0] will be
>> 0x112233445566778899aabbccddeeff00 regardless of host endianness. That
>> is, the least significant 8 bits of D0 will be (regs[0] & 0xff). (This
>> isn't the same number as if you do the union-type-punning thing with
>> union { uint64_t l; uint8_t b[8]; } and look at b[0].)

This example is confusing because I carefully said "64 bit write"
and then used a 128 bit constant. What I meant was:

 ie if you store 0x1122334455667788 as a 64 bit write
 to VFP register D0 then regs[0] will be
 0x1122334455667788 regardless of host endianness.

For 128 bit vectors, if you store
0x112233445566778899aabbccddeeff00 to Q0 then you get
regs[0] == 0x99aabbccddeeff00
regs[1] == 0x1122334455667788

(as is required architecturally in order for a subsequent guest
read from D0 to do the right thing).

-- PMM