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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [PATCH v5 25/45] target/arm: Implement BFMOPA, BFMOPS
Date: Thu, 7 Jul 2022 10:42:32 +0100	[thread overview]
Message-ID: <CAFEAcA8Ou2N9qJyvSy2wkpGtguCjJrA9YWoio4jsrv5VrNE3VQ@mail.gmail.com> (raw)
In-Reply-To: <20220706082411.1664825-26-richard.henderson@linaro.org>

On Wed, 6 Jul 2022 at 10:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper-sme.h    |  2 ++
>  target/arm/sme.decode      |  2 ++
>  target/arm/sme_helper.c    | 52 ++++++++++++++++++++++++++++++++++++++
>  target/arm/translate-sme.c | 30 ++++++++++++++++++++++
>  4 files changed, 86 insertions(+)
>
> diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
> index f50d0fe1d6..1d68fb8c74 100644
> --- a/target/arm/helper-sme.h
> +++ b/target/arm/helper-sme.h
> @@ -125,3 +125,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
>                     void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
>  DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
>                     void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
> +                   void, ptr, ptr, ptr, ptr, ptr, i32)
> diff --git a/target/arm/sme.decode b/target/arm/sme.decode
> index ba4774d174..afd9c0dffd 100644
> --- a/target/arm/sme.decode
> +++ b/target/arm/sme.decode
> @@ -73,3 +73,5 @@ ADDVA_d         11000000 11 01000 1 ... ... ..... 00 ...        @adda_64
>
>  FMOPA_s         10000000 100 ..... ... ... ..... . 00 ..        @op_32
>  FMOPA_d         10000000 110 ..... ... ... ..... . 0 ...        @op_64
> +
> +BFMOPA          10000001 100 ..... ... ... ..... . 00 ..        @op_32
> diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
> index 78ba34f3d2..4b437bb913 100644
> --- a/target/arm/sme_helper.c
> +++ b/target/arm/sme_helper.c
> @@ -981,3 +981,55 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
>          }
>      }
>  }
> +
> +/*
> + * Alter PAIR as needed for controlling predicates being false,
> + * and for NEG on an enabled row element.
> + */
> +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg)
> +{
> +    pair ^= neg;

You seem to be negating element 1 of row and col ('neg' here is
1 << 15 unless I've misread something, and it gets passed to
the calls for both the row and column data), but the pseudocode
says we want to negate element 0 and element 1 of row, and not
negate the col elements.

> +    if (!(pg & 1)) {
> +        pair &= 0xffff0000u;
> +    }
> +    if (!(pg & 4)) {
> +        pair &= 0x0000ffffu;
> +    }

The pseudocode sets the element to 0 if it is not
predicated, and then applies the negation second.

> +    return pair;
> +}
> +
> +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
> +                        void *vpm, uint32_t desc)
> +{
> +    intptr_t row, col, oprsz = simd_maxsz(desc);
> +    uint32_t neg = simd_data(desc) << 15;
> +    uint16_t *pn = vpn, *pm = vpm;
> +
> +    for (row = 0; row < oprsz; ) {
> +        uint16_t pa = pn[H2(row >> 4)];
> +        do {
> +            void *vza_row = vza + tile_vslice_offset(row);
> +            uint32_t n = *(uint32_t *)(vzn + row);

More missing H macros ?

> +
> +            n = f16mop_adj_pair(n, pa, neg);
> +
> +            for (col = 0; col < oprsz; ) {
> +                uint16_t pb = pm[H2(col >> 4)];
> +                do {
> +                    if ((pa & 0b0101) == 0b0101 || (pb & 0b0101) == 0b0101) {

The pseudocode test for "do we do anything" is
 (prow_0 && pcol_0) || (prow_1 && pcol_1)

but isn't this C expression doing
 (prow_0 && prow_1) || (pcol_0 && pcol_1) ?

> +                        uint32_t *a = vza_row + col;
> +                        uint32_t m = *(uint32_t *)(vzm + col);
> +
> +                        m = f16mop_adj_pair(m, pb, neg);
> +                        *a = bfdotadd(*a, n, m);
> +
> +                        col += 4;
> +                        pb >>= 4;
> +                    }
> +                } while (col & 15);
> +            }
> +            row += 4;
> +            pa >>= 4;
> +        } while (row & 15);
> +    }
> +}

thanks
-- PMM


  reply	other threads:[~2022-07-07  9:44 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-06  8:23 [PATCH v5 00/45] target/arm: Scalable Matrix Extension Richard Henderson
2022-07-06  8:23 ` [PATCH v5 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Richard Henderson
2022-07-06  8:23 ` [PATCH v5 02/45] target/arm: Add infrastructure for disas_sme Richard Henderson
2022-07-06  8:23 ` [PATCH v5 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Richard Henderson
2022-07-06 16:14   ` Peter Maydell
2022-07-06  8:23 ` [PATCH v5 04/45] target/arm: Mark ADR as non-streaming Richard Henderson
2022-07-06  8:23 ` [PATCH v5 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 07/45] target/arm: Mark PMULL, FMMLA " Richard Henderson
2022-07-06 16:13   ` Peter Maydell
2022-07-06  8:23 ` [PATCH v5 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 10/45] target/arm: Mark string/histo/crypto " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 11/45] target/arm: Mark gather/scatter load/store " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 12/45] target/arm: Mark gather prefetch " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 13/45] target/arm: Mark LDFF1 and LDNF1 " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 14/45] target/arm: Mark LD1RO " Richard Henderson
2022-07-06  8:23 ` [PATCH v5 15/45] target/arm: Add SME enablement checks Richard Henderson
2022-07-06  8:23 ` [PATCH v5 16/45] target/arm: Handle SME in sve_access_check Richard Henderson
2022-07-06  8:23 ` [PATCH v5 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Richard Henderson
2022-07-06  8:23 ` [PATCH v5 18/45] target/arm: Implement SME ZERO Richard Henderson
2022-07-06  8:23 ` [PATCH v5 19/45] target/arm: Implement SME MOVA Richard Henderson
2022-07-06 16:47   ` Peter Maydell
2022-07-07  0:56     ` Richard Henderson
2022-07-06  8:23 ` [PATCH v5 20/45] target/arm: Implement SME LD1, ST1 Richard Henderson
2022-07-06 16:50   ` Peter Maydell
2022-07-06  8:23 ` [PATCH v5 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Richard Henderson
2022-07-06  8:23 ` [PATCH v5 22/45] target/arm: Implement SME LDR, STR Richard Henderson
2022-07-06  8:23 ` [PATCH v5 23/45] target/arm: Implement SME ADDHA, ADDVA Richard Henderson
2022-07-06 16:53   ` Peter Maydell
2022-07-06  8:23 ` [PATCH v5 24/45] target/arm: Implement FMOPA, FMOPS (non-widening) Richard Henderson
2022-07-07  9:26   ` Peter Maydell
2022-07-06  8:23 ` [PATCH v5 25/45] target/arm: Implement BFMOPA, BFMOPS Richard Henderson
2022-07-07  9:42   ` Peter Maydell [this message]
2022-07-08 14:42     ` Richard Henderson
2022-07-06  8:23 ` [PATCH v5 26/45] target/arm: Implement FMOPA, FMOPS (widening) Richard Henderson
2022-07-07  9:50   ` Peter Maydell
2022-07-06  8:23 ` [PATCH v5 27/45] target/arm: Implement SME integer outer product Richard Henderson
2022-07-06  8:23 ` [PATCH v5 28/45] target/arm: Implement PSEL Richard Henderson
2022-07-06  8:23 ` [PATCH v5 29/45] target/arm: Implement REVD Richard Henderson
2022-07-06  8:23 ` [PATCH v5 30/45] target/arm: Implement SCLAMP, UCLAMP Richard Henderson
2022-07-06  8:23 ` [PATCH v5 31/45] target/arm: Reset streaming sve state on exception boundaries Richard Henderson
2022-07-06  8:23 ` [PATCH v5 32/45] target/arm: Enable SME for -cpu max Richard Henderson
2022-07-06  8:23 ` [PATCH v5 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Richard Henderson
2022-07-06  8:24 ` [PATCH v5 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls Richard Henderson
2022-07-06  8:24 ` [PATCH v5 35/45] linux-user/aarch64: Add SM bit to SVE signal context Richard Henderson
2022-07-06 16:54   ` Peter Maydell
2022-07-06  8:24 ` [PATCH v5 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Richard Henderson
2022-07-06  8:24 ` [PATCH v5 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Richard Henderson
2022-07-06 16:55   ` Peter Maydell
2022-07-06  8:24 ` [PATCH v5 38/45] linux-user/aarch64: Verify extra record lock succeeded Richard Henderson
2022-07-06  8:24 ` [PATCH v5 39/45] linux-user/aarch64: Move sve record checks into restore Richard Henderson
2022-07-06  8:24 ` [PATCH v5 40/45] linux-user/aarch64: Implement SME signal handling Richard Henderson
2022-07-06  8:24 ` [PATCH v5 41/45] linux-user: Rename sve prctls Richard Henderson
2022-07-06  8:24 ` [PATCH v5 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Richard Henderson
2022-07-06  8:24 ` [PATCH v5 43/45] target/arm: Only set ZEN in reset if SVE present Richard Henderson
2022-07-06  8:24 ` [PATCH v5 44/45] target/arm: Enable SME for user-only Richard Henderson
2022-07-06  8:24 ` [PATCH v5 45/45] linux-user/aarch64: Add SME related hwcap entries Richard Henderson
2022-07-07  9:52 ` [PATCH v5 00/45] target/arm: Scalable Matrix Extension Peter Maydell

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