From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: Re: [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
Date: Sat, 2 Mar 2024 10:59:19 +0000 [thread overview]
Message-ID: <CAFEAcA8PB=601P-sWbBfVbDr1DMyLkZ0V6aseEX5Z=s=Bv0v0A@mail.gmail.com> (raw)
In-Reply-To: <97dbadc0-a9f0-4c32-abb1-7613380e2a5c@linaro.org>
On Fri, 1 Mar 2024 at 21:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/1/24 08:32, Peter Maydell wrote:
> > +static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
> > +{
> > + if ((env->cp15.scr_el3 & SCR_ECVEN) &&
> > + FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
> > + arm_is_el2_enabled(env) &&
> > + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
>
> arm_hcr_el2_eff checks arm_is_el2_enabled and returns 0 if disabled.
Yes, and if it returns 0 then the E2H|TGE bits will not be E2H|TGE,
and so we'll incorrectly apply the CNTPOFF value. We can only elide
the arm_is_el2_enabled() test if we're checking for some HCR bit
being 1. (I also initially thought the arm_is_el2_enabled() check was
redundant and then found it was not :-))
-- PMM
next prev parent reply other threads:[~2024-03-02 11:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-01 18:32 [PATCH 0/8] target/arm: Implement FEAT_ECV (Enhanced Counter Virtualization) Peter Maydell
2024-03-01 18:32 ` [PATCH 1/8] target/arm: Move some register related defines to internals.h Peter Maydell
2024-03-01 19:03 ` Philippe Mathieu-Daudé
2024-03-01 21:01 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 2/8] target/arm: Timer _EL02 registers UNDEF for E2H == 0 Peter Maydell
2024-03-01 21:08 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 3/8] target/arm: use FIELD macro for CNTHCTL bit definitions Peter Maydell
2024-03-01 19:04 ` Philippe Mathieu-Daudé
2024-03-01 21:10 ` Richard Henderson
2024-03-01 21:19 ` Richard Henderson
2024-03-04 13:21 ` Peter Maydell
2024-03-04 17:02 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Peter Maydell
2024-03-01 21:11 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 5/8] target/arm: Implement new FEAT_ECV trap bits Peter Maydell
2024-03-01 21:37 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 6/8] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 Peter Maydell
2024-03-01 21:41 ` Richard Henderson
2024-03-01 18:32 ` [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling Peter Maydell
2024-03-01 21:54 ` Richard Henderson
2024-03-02 10:59 ` Peter Maydell [this message]
2024-03-01 18:32 ` [PATCH 8/8] target/arm: Enable FEAT_ECV for 'max' CPU Peter Maydell
2024-03-01 19:05 ` Philippe Mathieu-Daudé
2024-03-01 21:58 ` Richard Henderson
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